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doonny / PipeCNN

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Apache License 2.0
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HW Configuration for DE1SOC to reduce "Logic utilization" #46

Closed ArjunaDeSoysa closed 6 years ago

ArjunaDeSoysa commented 6 years ago

Dear Prof. Wang,

I use De1-SoC and I changed,

VEC_SIZE  = 8
LANE_NUM = 8 
CONV_GP_SIZE_X = 7  , as the user instruction.

and PLATFORM = arm32 and FLOW = hw

then it's Estimated Resource Usage Summary shows that, Logic utilization = 111%

Then I got the following error even-though the resources of the device is not fully used up. kernel cannot fit into device

My question is, Is there any other ways to reduce "Logic utilization", except reduce "LANE NUM" ?

Thank You.

doonny commented 6 years ago

you could also use a smaller value of VEC_SIZE

ArjunaDeSoysa commented 6 years ago

@doonny, I mean except reduce the value of LANE_NUM and VEC_SIZE , Is there any other ways to reduce Logic utilization? because I need to get lowest Excution Time.(by reduce LANE_NUM=4, i got just around 450 ms )

Thank You.

doonny commented 6 years ago

Please do not use the '--profile' option when you compile the kernel. That will cost you a lot of LUTs. You should get the same results as we do.

ArjunaDeSoysa commented 6 years ago

Ok. I got it. now its complete in 149ms. Thank You Professor @doonny .