order of System.Runtime.Intrinsics.X86.AVX512F[.VL].GetMantissa()'s interval and sign flags is undocumented

[twest820]

As noted in https://github.com/dotnet/runtime/issues/86168, the float and double overloads of the 128, 256, and 512 bit GetMantissa() methods differ from the Intel intrinsics' signatures of the form

__m256 _mm256_getmant_ps (__m256 a, _MM_MANTISSA_NORM_ENUM interv, _MM_MANTISSA_SIGN_ENUM sc)

in that the two enums are collapsed into a control byte

public static Vector256<float> GetMantissa(Vector256<float> value, [ConstantExpected(Max = (byte)(0x0F))] byte control)

avx512fintrin.h defines the interval and sign enums from zero to three as

enum _MM_MANTISSA_NORM_ENUM { _MM_MANT_NORM_1_2 , _MM_MANT_NORM_p5_2 , _MM_MANT_NORM_p5_1 , _MM_MANT_NORM_p75_1p5 }
enum _MM_MANTISSA_SIGN_ENUM { _MM_MANT_SIGN_src , _MM_MANT_SIGN_zero , _MM_MANT_SIGN_nan }

indicating they're packed into the lower four bits of control in the C# API. However, the current docs and source code both omit both interv and sc from the intrinsics' signatures and don't say which enum goes in bits 0:1 and which in 2:3 of control.

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Issue Details

---

As noted in https://github.com/dotnet/runtime/issues/86168, the `float` and `double` overloads of the 128, 256, and 512 bit `GetMantissa()` methods differ from the Intel intrinsics' signatures of the form ``` __m256 _mm256_getmant_ps (__m256 a, _MM_MANTISSA_NORM_ENUM interv, _MM_MANTISSA_SIGN_ENUM sc) ``` in that the two enums are collapsed into a control byte ``` public static Vector256 GetMantissa(Vector256 value, [ConstantExpected(Max = (byte)(0x0F))] byte control) ``` avx512fintrin.h defines the interval and sign enums from zero to three as ``` enum _MM_MANTISSA_NORM_ENUM { _MM_MANT_NORM_1_2 , _MM_MANT_NORM_p5_2 , _MM_MANT_NORM_p5_1 , _MM_MANT_NORM_p75_1p5 } enum _MM_MANTISSA_SIGN_ENUM { _MM_MANT_SIGN_src , _MM_MANT_SIGN_zero , _MM_MANT_SIGN_nan } ``` indicating they're packed into the lower four bits of `control` in the C# API. However, [the current docs](https://learn.microsoft.com/en-us/dotnet/api/system.runtime.intrinsics.x86.avx512f.vl.getmantissa?view=net-8.0) and [source code](https://github.com/dotnet/runtime/blob/main/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/X86/Avx512F.cs) both omit both `interv` and `sc` from the intrinsics' signatures and don't say which enum goes in bits 0:1 and which in 2:3 of `control`.

Author:	twest820
Assignees:	-
Labels:	`untriaged`, `Pri3`, `area-System.Runtime.Intrinsics`, `needs-area-label`
Milestone:	-

[tannergooding]

The control byte exactly matches the imm8 encoded by the actual instruction, whose documentation is available via the underlying architecture manual's for the platform, such as: https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html or https://www.amd.com/en/search/documentation/hub.html#sortCriteria=%40amd_release_date%20descending&f-amd_document_location=AMD.com&f-amd_document_type=Programmer%20References&f-amd_archive_status=Active

The actual documentation for the instructions is copywritten and cannot be reproduced without permission. Getting permission is not as trivial as one might think and is a long-standing issue that is being tracked.