Open twest820 opened 10 months ago
I couldn't figure out the best area label to add to this issue. If you have write-permissions please help me learn by adding exactly one area label.
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Author: | twest820 |
---|---|
Assignees: | - |
Labels: | `untriaged`, `Pri3`, `area-System.Runtime.Intrinsics`, `needs-area-label` |
Milestone: | - |
The control byte exactly matches the imm8
encoded by the actual instruction, whose documentation is available via the underlying architecture manual's for the platform, such as: https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html or https://www.amd.com/en/search/documentation/hub.html#sortCriteria=%40amd_release_date%20descending&f-amd_document_location=AMD.com&f-amd_document_type=Programmer%20References&f-amd_archive_status=Active
The actual documentation for the instructions is copywritten and cannot be reproduced without permission. Getting permission is not as trivial as one might think and is a long-standing issue that is being tracked.
As noted in https://github.com/dotnet/runtime/issues/86168, the
float
anddouble
overloads of the 128, 256, and 512 bitGetMantissa()
methods differ from the Intel intrinsics' signatures of the formin that the two enums are collapsed into a control byte
avx512fintrin.h defines the interval and sign enums from zero to three as
indicating they're packed into the lower four bits of
control
in the C# API. However, the current docs and source code both omit bothinterv
andsc
from the intrinsics' signatures and don't say which enum goes in bits 0:1 and which in 2:3 ofcontrol
.