Updating coredistools

[BruceForstall]

What should be included in the next update of the coredistools library (used for x86/x64 GC stress, R2RDump disassembly, superpmi asm diffs, RyuJIT "late disassembler", ILC (?), and possibly more)?

Some proposals:

1. Update LLVM from 17.0.6 to 19.1.0 (or whatever is latest when we finally update): https://github.com/llvm/llvm-project/releases.
2. Add LoongArch and RISC-V disassemblers to the standard set built on win-x64, win-arm64, etc. (Allows for superpmi asm diffs using cross compilers, for example.)
3. Does the latest LLVM contain support for the latest AVX-512? AVX10? Intel APX? Arm SVE/SVE2/SSVE/SME? Other new ISA extensions? (If not, is new LLVM ISA support for desired ISAs expected soon?)

Cordistools.cpp currently tweaks the "features string" when creating the disassembler, to create a better set of ISAs for disassembly:

  if (TheTargetArch == Target_Arm64) {
    // Enable all features for disassembly. Setting a specific advanced CPU enables all the architecture
    // features for that CPU (e.g., `Mcpu = "neoverse-n2"`), but we want to use the "meta" feature
    // string "+all" to just enable all features, even those not implemented in any current CPU.
    FeaturesStr = "+all";
  } else if (TheTargetArch == Target_RiscV64) {
    FeaturesStr = "+m,+a,+f,+d,+c,+zicsr,+zifencei";  // RV64GC
  }

Notably, when this was done, "+all" for arm64 was not in "great" shape.

Is this still the correct set, for LLVM 19.1.0 (and beyond)?

Is there any pressing need to either update coredistools, or wait to update it?

Comments?

@dotnet/jit-contrib @dotnet/samsung @shushanhf @dotnet/crossgen-contrib @khushal1996 @DeepakRajendrakumaran @anthonycanino

[shushanhf]

2. Add LoongArch and RISC-V disassemblers to the standard set built on win-x64, win-arm64, etc. (Allows for superpmi asm diffs using cross compilers, for example.)

@BruceForstall Thanks very much for adding LoongArch. For LoongArch, if there are some work to do, you can tell me to do that.

Update LLVM from 17.0.6 to 19.1.0 (or whatever is latest when we finally update): https://github.com/llvm/llvm-project/releases.

It's ok for LoongArch.

[BruceForstall]

Also @dotnet/arm64-contrib

[tomeksowi]

Thanks for adding RISC-V disasm to the standard set. Clang 19 should be ok.

EDIT: I'll check if "+all" works now for RISC-V

[tomeksowi]

Is there any pressing need to either update coredistools, or wait to update it?

Not really from RISC-V. We will be adding RVA22 profile extensions somewhere in 2025, but RV64GC is the correct set for now.

[tomeksowi]

EDIT: I'll check if "+all" works now for RISC-V

Nope, it's AArch64 only: '+all' is not a recognized feature for this target (ignoring feature)

But while I'm here, I'll add more extensions for RISC-V to future-proof.

[anthonycanino]

Hi Bruce, I will check internally and get back to you on ISA support in LLVM latest. I believe by just using latest we should be fine, but will confirm whether we have any pending work.

[anthonycanino]

@BruceForstall latest LLVM disassembler should have full support for APX and AVX10.2. I think we are good.