Open EgorBo opened 7 months ago
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Hi, I'd like to attempt this issue if no one else is, thanks!
I gave this fix a try, it seems to work for ARM, generating the bics instruction without a cmp.
However, on x_arch, I can get the andn
instruction to be generated when hw intrinsics are enabled, but I'm unable to get the not
test
structure.
I can't figure out how to transform the tree of CMP(AND(NOT(x), y)) to turn into a test. There are options for GT_TEST_EQ and GT_TEST_NE, neither of which are what I want. I just want a TEST(NOT(x), y) structure where y is not necessarily 0 (TEST_EQ and TEST_NE both assume the second operand is 0). When I change the node type to GT_TEST, there's assert errors
Any tips that people can share about getting past this?
Hi @EgorBo, sorry to ping you, I figured out how to do the optimization change but I'm not sure how to interpret the pipeline results as I see some of them timed out. I also see a couple that are formatting related, but I can't seem to access the artifacts as described in the logs.
Here's the pull request: https://github.com/dotnet/runtime/pull/103868
Edit, to be more specific, I see some of these errors:
Assertion failed 'OperIs(GT_CNS_INT)' in 'System.Decimal:IsEvenInteger(System.Decimal):ubyte'
I tried to find this assert, wasn't sure which it was. I also tried to JitDisasm this, but couldn't get it to work. In addition, I am looking for a flag to set (but not sure what exists) that will make the bics save the result to wzr instead of an actual register
Thank you very much!
Noticed in https://github.com/dotnet/runtime/pull/100999:
Codegen on arm64:
Expected codegen:
x64 is suboptimal for it as well, current codegen:
^ should be not + test.