douggilliland / R32V2020

My 32-bit RISC CPU for smallish FPGAs
GNU General Public License v3.0
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assembler mis error #36

Closed douggilliland closed 5 years ago

douggilliland commented 5 years ago

@mjgpy3

C:\Users\HPz420\Documents\GitHub\R32V2020\VHDL\Programs\C010-CCR_Test>..\..\..\Assembler\assembler.py C010-CCR_Test.asm
Expected 3 arguments after op but got 3

Line 6:
        cmp r3,r0,r0

I miscoded it with three opcodes but the compare just has 2 opcodes.

Not a serious error just an error in the error message since this compiles without error.

    cmp r0,r0

Most of the opcodes in the ALU take 3 args but CMP takes 2. Sorry about the asymmetry.

douggilliland commented 5 years ago

Checked in C010 with 2 args. You can break it as above ;)

Thank you for your work on this. It's so easy to write code now.