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douggilliland / R32V2020

My 32-bit RISC CPU for smallish FPGAs
GNU General Public License v3.0
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Shift operations two two operators #41

Closed douggilliland closed 5 years ago

douggilliland commented 5 years ago

@mjgpy3 These opcodes should have a source and destination pair

ALU UN_R1_DEST Shift left by one LS1
ALU UN_R1_DEST Shift right by one RS1
ALU UN_R1_DEST Rotate left by one LR1
ALU UN_R1_DEST Rotate right by one RR1
ALU UN_R1_DEST Right arithmetic shift RA1

ex: rs1 r8,r9 ; shift r9 to the right by one bit and store in r8

douggilliland commented 5 years ago

And they should have an implicit r1 in the D19..D16 position. The r1 is the shift count. For now, I only do shifts by 1. But if I later added a count into a register I could do longer shifts. Would need to implement a barrel shifter in hardware to do that.

douggilliland commented 5 years ago

@mjgpy3 Put in a patch that works for now. Changed as follows:

ALU | UN_DEST | Shift left by one | LS1 ALU | UN_DEST | Shift right by one | RS1 ALU | UN_DEST | Rotate left by one | LR1 ALU | UN_DEST | Rotate right by one | RR1 ALU | UN_DEST | Right arithmetic shift | RA1

Would prefer if this used r1 as second src but it works for now.

douggilliland commented 5 years ago

@mjgpy3 Better yet, I just changed the syntax to require both operators.

ALU | BIN_DEST | Shift left by one | LS1 ALU | BIN_DEST | Shift right by one | RS1 ALU | BIN_DEST | Rotate left by one | LR1 ALU | BIN_DEST | Rotate right by one | RR1 ALU | BIN_DEST | Right arithmetic shift | RA1