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douggilliland / R32V2020

My 32-bit RISC CPU for smallish FPGAs
GNU General Public License v3.0
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Data packing #49

Open douggilliland opened 5 years ago

douggilliland commented 5 years ago

Unnecessary enhancement. All values use a long location regardless of their length. Could use space more efficiently (unnecessary enhancement). Just noting for possible future enhancements.

If we implement better packing we still need to make sure that when we go to a new data type that we long word align the addresses.

firstLong: .long 0x00000001 secondLong: .long 0x00000002 firstShort: .short 0x1234 secondShort: .short 0x5678 firstByte: .byte 0x99 secondByte: .byte 0x88 thirdByte: .byte 0x77 fourthByte: .byte 0x66

start: 00000000 42800000 lix r8,firstLong.lower 00000001 42800004 lix r8,secondLong.lower 00000002 42800008 lix r8,firstShort.lower 00000003 4280000C lix r8,secondShort.lower 00000004 42800010 lix r8,firstByte.lower 00000005 42800014 lix r8,secondByte.lower 00000006 42800018 lix r8,thirdByte.lower 00000007 4280001C lix r8,fourthByte.lower

douggilliland commented 5 years ago

Optimizing above would be:

00000002 42800008 lix r8,firstShort.lower 00000003 4280000A lix r8,secondShort.lower 00000004 4280000C lix r8,firstByte.lower 00000005 4280000D lix r8,secondByte.lower 00000006 4280000E lix r8,thirdByte.lower 00000007 4280000F lix r8,fourthByte.lower

douggilliland commented 5 years ago

It would be a bit tricky to test and make sure the address is long word aligned. .long has to always be long word aligned. .short has to always be short word aligned. .byte can be any aligned.