Closed douggilliland closed 5 years ago
Since I changed the assembler instructions some of them now use reserved words. So I added _OP to the operand in the generate constants file. (Changed assembler.py).
For instance OR is a reserved keyword in VHDL. Got this to work.
Since I changed the assembler instructions some of them now use reserved words. So I added _OP to the operand in the generate constants file. (Changed assembler.py).
For instance OR is a reserved keyword in VHDL. Got this to work.