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douggilliland / R32V2020

My 32-bit RISC CPU for smallish FPGAs
GNU General Public License v3.0
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ANSI Screen Performance Measurements #54

Closed douggilliland closed 5 years ago

douggilliland commented 5 years ago

@mjgpy3 This is not an issues, just a note.

My original goal for making the R32V2020 RISC CPU was to measure the performance of the ANSI Screen design. The Multicomp project used slow 8-bit CPUs and they couldn't keep up with the speed of the ANSI Screen.

R32V2020 is more than fast enough to write data to the screen for good benchmarks. Added performance numbers here if you want to see them: https://github.com/douggilliland/R32V2020/wiki/ANSI-Terminal-with-UART-Interface#performance

They are really impressive.

douggilliland commented 5 years ago

@mjgpy3 Of course my other goal was to do a decent sized FPGA project to reacquaint myself with VHDL. I've definitely got that down now.