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dpaul24 / hdmi_pass_through_ZyboZ7-10

This is a simple design example showing how a HDMI signal can be passed through a FPGA without any type of processing on it. The Digilent Zybo Z7-10 development board has been used.
MIT License
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HDMI Pass through doesn't work on Zybo Z7-10 #2

Open tnguyen-tx opened 3 months ago

tnguyen-tx commented 3 months ago

Hi @dpaul24, I've tried to replicate hdmi pass through project from your repo but got some critical warnings I don't know how to solve and don't know why that happened. Could you help to take a look? So far I don't see much of difference from my block design to yours. My block design image clocking wizard setting image image dvi2rgb block image rgb2dvi block image

Constraint file:

Clock signal

set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sys_clk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk

create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sys_clk }];

HDMI RX

set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_scl_io }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl

set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_sda_io }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda

Clock signal

set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {sys_clk}]; #IO_L12P_T1_MRCC_35 Sch=sysclk create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports {sys_clk}];

System Reset

set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { reset_rtl }]; #IO_L12N_T1_MRCC_35 Sch=btn[0] set_false_path -from [get_ports reset_rtl]

< 80MHz TMDS clock

create_clock -period 13.468 -waveform {0.000 6.734} [get_ports TMDS_Clk_p_i]

set_property -dict {PACKAGE_PIN U19 IOSTANDARD TMDS_33} [get_ports {TMDS_Clk_n_i}]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n set_property -dict {PACKAGE_PIN U18 IOSTANDARD TMDS_33} [get_ports {TMDS_Clk_p_i}]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p

set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_n_i[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0] set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_p_i[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0] set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_n_i[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1] set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_p_i[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1] set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_n_i[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2] set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_p_i[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]

set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { aRst_0 }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd

set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { reset_rtl }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd

HDMI RX CEC (Zybo Z7-20 only)

set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec

HDMI TX

set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl

set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda

set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { TMDS_Clk_n_o }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { TMDS_Clk_p_o }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_n_o[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0] set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_p_o[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0] set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_n_o[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1] set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_p_o[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1] set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_n_o[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2] set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_p_o[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]

set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd

set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd_o }]; set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { scl_io }] set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { sda_io }]

The video processing module is just a pass through unit.

`timescale 1ns / 1ps

module video_processing( input wire [23:0] vid_data_i, input wire pHSync_i, input wire pVSync_i, input wire pVDE_i, input wire clk_pix_i, output wire[23:0] vid_data_o, output wire pHSync_o, output wire pVSync_o, output wire pVDE_o, output wire clk_pix_o );

assign vid_data_o = vid_data_i; assign pHSync_o = pHSync_i; assign pVSync_o = pVSync_i; assign pVDE_o = pVDE_i; assign clk_pix_o = clk_pix_i;

endmodule

Log file:

CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_refclk'. The XDC file c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_refclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_pixclk'. The XDC file c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_pixclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. Parsing XDC File [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/dvi2rgb.xdc] for cell 'U0' Finished Parsing XDC File [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/dvi2rgb.xdc] for cell 'U0' Parsing XDC File [C:/Users/thuyn/video_filter/video_filter.runs/dvi2rgb_0_synth_1/dont_touch.xdc] Finished Parsing XDC File [C:/Users/thuyn/video_filter/video_filter.runs/dvi2rgb_0_synth_1/dont_touch.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/thuyn/video_filter/video_filter.runs/dvi2rgb_0_synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/dvi2rgb_0_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/dvi2rgb_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Timing 38-2] Deriving generated clocks Parsing XDC File [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc] for cell 'U0' WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:10] WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q" && IS_SEQUENTIAL }'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:10] CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}]'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:10] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:11] WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q" && IS_SEQUENTIAL }'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:11] CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}]'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:11] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:12] WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q" && IS_SEQUENTIAL }'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:12] CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}]'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:12] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical -filter { NAME =~ "allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:13] WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical -filter {NAME =~ "allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D"}'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:13] CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins -hierarchical -filter { NAME =~ "allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}]'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:13]

dpaul24 commented 3 months ago

Hi, As far as I remember I do not have any ila_*clock in my design but you have them. Only looking at the messages you have posted here, that is one difference I can see. You need to insert ILAs only for debugging. Removing ILAs might solve the Critical Warnings. Regards,Debayan

Yahoo Mail: Search, organise, conquer

On Fri, 5 Jul 2024 at 21:42, Thuy @.***> wrote:

Hi @dpaul24, I've tried to replicate hdmi pass through project from your repo but got some critical warnings I don't know how to solve and don't know why that happened. Could you help to take a look? So far I don't see much of difference from my block design to yours. My block design image.png (view on web) clocking wizard setting image.png (view on web) image.png (view on web) dvi2rgb block image.png (view on web) rgb2dvi block image.png (view on web)

Constraint file:

Clock signal

set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sys_clk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk

create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sys_clk }];

HDMI RX

set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_scl_io }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl

set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_sda_io }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda

Clock signal

set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {sys_clk}]; #IO_L12P_T1_MRCC_35 Sch=sysclk create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports {sys_clk}];

System Reset

set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { reset_rtl }]; #IO_L12N_T1_MRCC_35 Sch=btn[0] set_false_path -from [get_ports reset_rtl]

< 80MHz TMDS clock

create_clock -period 13.468 -waveform {0.000 6.734} [get_ports TMDS_Clk_p_i]

set_property -dict {PACKAGE_PIN U19 IOSTANDARD TMDS_33} [get_ports {TMDS_Clk_n_i}]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n set_property -dict {PACKAGE_PIN U18 IOSTANDARD TMDS_33} [get_ports {TMDS_Clk_p_i}]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p

set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_n_i[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0] set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_p_i[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0] set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_n_i[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1] set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_p_i[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1] set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_n_i[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2] set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_p_i[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]

set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { aRst_0 }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd

set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { reset_rtl }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd

HDMI RX CEC (Zybo Z7-20 only)

set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec

HDMI TX

set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl

set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda

set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { TMDS_Clk_n_o }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { TMDS_Clk_p_o }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_n_o[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0] set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_p_o[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0] set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_n_o[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1] set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_p_o[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1] set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_n_o[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2] set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { TMDS_Data_p_o[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]

set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd

set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd_o }]; set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { scl_io }] set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { sda_io }]

The video processing module is just a pass through unit.

`timescale 1ns / 1ps

module video_processing( input wire [23:0] vid_data_i, input wire pHSync_i, input wire pVSync_i, input wire pVDE_i, input wire clk_pix_i, output wire[23:0] vid_data_o, output wire pHSync_o, output wire pVSync_o, output wire pVDE_o, output wire clk_pix_o );

assign vid_data_o = vid_data_i; assign pHSync_o = pHSync_i; assign pVSync_o = pVSync_i; assign pVDE_o = pVDE_i; assign clk_pix_o = clk_pix_i;

endmodule

Log file:

CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_refclk'. The XDC file c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_refclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_pixclk'. The XDC file c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_pixclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. Parsing XDC File [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/dvi2rgb.xdc] for cell 'U0' Finished Parsing XDC File [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/dvi2rgb.xdc] for cell 'U0' Parsing XDC File [C:/Users/thuyn/video_filter/video_filter.runs/dvi2rgb_0_synth_1/dont_touch.xdc] Finished Parsing XDC File [C:/Users/thuyn/video_filter/video_filter.runs/dvi2rgb_0_synth_1/dont_touch.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/thuyn/video_filter/video_filter.runs/dvi2rgb_0_synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/dvi2rgb_0_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/dvi2rgb_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Timing 38-2] Deriving generated clocks Parsing XDC File [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc] for cell 'U0' WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:10] WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q" && IS_SEQUENTIAL }'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:10] CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}]'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:10] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:11] WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q" && IS_SEQUENTIAL }'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:11] CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}]'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:11] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:12] WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q" && IS_SEQUENTIAL }'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:12] CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins -hierarchical -filter { NAME =~ "ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}]'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:12] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical -filter { NAME =~ "allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:13] WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical -filter {NAME =~ "allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D"}'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:13] CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins -hierarchical -filter { NAME =~ "allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[].U_ALL_SRL_SLICE/u_srl/S/CLK"}]'. [c:/Users/thuyn/video_filter/video_filter.gen/sources_1/ip/dvi2rgb_0/src/ila_timing_workaround.xdc:13]

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