dpretet axi-crossbar issues - Githubissues

dpretet / axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

MIT License

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issues

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AXI protocol violation

#19 dpretet opened 4 days ago
0
Feature: Support address translation

#18 dpretet opened 2 weeks ago
0
Fearure: Cyclic dependency avoidance

#17 dpretet opened 2 weeks ago
0
Feature: Support dynamic priority per master

#16 dpretet opened 3 weeks ago
0
Feature: Secure/Non-secure memory map

#15 dpretet opened 3 weeks ago
0
Feature: Support early write response

#14 dpretet opened 5 months ago
0
Feature: Provide a RTL generator

#13 dpretet opened 5 months ago
0
Feature: Support any number of slave / master interfaces

#12 dpretet opened 5 months ago
0
Feature: Debug interface

#11 dpretet opened 5 months ago
0
Feature: Read-only or write-only interfaces

#10 dpretet opened 5 months ago
0
Feature: Implement AXI completion queue per ID to ensure ordering rules

#9 dpretet opened 5 months ago
0
Feature: Timeout events handling

#8 dpretet opened 7 months ago
0
Is there a porblem with the push signal of SCFIFO module？

#7 jingzhizhang closed 2 years ago
3
Remove base address in master interfaces

#6 dpretet closed 2 years ago
0
multi master transfer discussion

#5 vincentliu84 closed 2 years ago
9
Manage request targeting unspecified address mapping

#4 dpretet closed 2 years ago
1
AXI-4 Lite transfer fail (Master write)

#3 vincentliu84 closed 2 years ago
9
duplicated identifier defined

#2 vincentliu84 closed 2 years ago
5
compile error using xcelium

#1 vincentliu84 closed 3 years ago
1