Closed rtc-draper closed 10 years ago
This bug was in the LDRi12 implementation (line 220), here: https://github.com/draperlaboratory/fracture/blob/master/lib/Target/ARM/ARMInvISelDAG.cpp#L220
LDRi12 has a valid pattern (see ARMGenInvISelDAG.cpp):
/*2079*/ OPC_CheckOpcode, TARGET_VAL(ARM::LDRi12),
/*2082*/ OPC_RecordNode, // #0 = 'LDRi12' chained node
/*2083*/ OPC_MoveChild, 1,
/*2085*/ OPC_RecordNode, // #1 = $base
/*2086*/ OPC_MoveParent,
/*2087*/ OPC_MoveChild, 2,
/*2089*/ OPC_RecordNode, // #2 = $offsimm
/*2090*/ OPC_MoveParent,
/*2091*/ OPC_MoveChild, 3,
/*2093*/ OPC_RecordNode, // #3 = $p
/*2094*/ OPC_MoveParent,
/*2095*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectAddrModeImm12:$addr #4 #5
/*2098*/ OPC_EmitMergeInputChains1_0,
/*2099*/ OPC_EmitNode, TARGET_VAL(ISD::LOAD), 0|OPFL_Chain|OPFL_MemRefs,
1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1, // Results = #6
/*2107*/ OPC_CompleteMatch, 1, 0,
Sample instruction (the one causing the crash):
%R3<def> = LDRi12 %R11, 4294967280, pred:14, pred:%noreg; mem:LD4[<unknown>](align=0) dbg::34012
Which works out to line 0x84DC:
000084DC: 10 30 1B E5 ldr r3, [r11, #-16]
Which gets translated too:
%R11_7 = load i32* %R11, !dbg !126
%R11_8 = add i32 %R11_7, -16, !dbg !126
%R11_9 = inttoptr i32 %R11_8 to i32*, !dbg !126
%R11_10 = load i32* %R11_9, !dbg !126
store i32 %R11_10, i32* %R3, !dbg !126
Which loads from memory address r11-16 and stores it in r3 (looks right to me).
Please let me know why you thought you needed to implement it -- (maybe there's a test case where the Tablegen backend is failing!)
See 910b5d2fe64ce5a5734b3364ef679053b57e5138 for fix.
Someone broke the build on master. Please do your dev in a branch...