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draperlaboratory / fracture

an architecture-independent decompiler to LLVM IR
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Broken build #35

Closed rtc-draper closed 10 years ago

rtc-draper commented 10 years ago

Someone broke the build on master. Please do your dev in a branch...

$ ./Debug+Asserts/bin/fracture-cl -mattr=v6 ./samples/arm/fib_armel
MCDirector: Using Triple: arm-unknown-unknown
MCDirector: Using CPU: generic
MCDirector: Using Features: +v6
Disassembler: Setting Section .text
Triple: arm-unknown-unknown
CPU: generic
Debug+Asserts/bin/fracture-cl> dec main
0  fracture-cl     0x00000000017991ce _ZN4llvm3sys15PrintStackTraceEP8_IO_FILE + 46
1  fracture-cl     0x000000000179948b
2  fracture-cl     0x000000000179ab0e
3  libpthread.so.0 0x00007f07ccdbf760
4  fracture-cl     0x0000000000640f06
5  fracture-cl     0x000000000064117a
6  fracture-cl     0x0000000000f211d0 _ZN4llvm12SelectionDAG7getLoadENS_3EVTENS_5SDLocENS_7SDValueES3_NS_18MachinePointerInfoEbbbjPKNS_6MDNodeES7_ + 144
7  fracture-cl     0x0000000000673202 _ZN8fracture13ARMInvISelDAG12TransmogrifyEPN4llvm6SDNodeE + 6210
8  fracture-cl     0x000000000063b57b _ZN8fracture10Decompiler19decompileBasicBlockEPN4llvm17MachineBasicBlockEPNS1_8FunctionE + 811
9  fracture-cl     0x000000000063a725 _ZN8fracture10Decompiler17decompileFunctionEj + 917
10 fracture-cl     0x000000000063a01d _ZN8fracture10Decompiler9decompileEj + 77
11 fracture-cl     0x00000000006274e6
12 fracture-cl     0x0000000000639b25 _ZN10CmdExprAST7CodegenEv + 373
13 fracture-cl     0x0000000000635884 _ZN8Commands17handleCommandLineEv + 132
14 fracture-cl     0x0000000000635935 _ZN8Commands8runShellESs + 165
15 fracture-cl     0x00000000006264ac main + 684
16 libc.so.6       0x00007f07cbdd1c85 __libc_start_main + 245
17 fracture-cl     0x0000000000624629
Stack dump:
0.      Program arguments: ./Debug+Asserts/bin/fracture-cl -mattr=v6 ./samples/arm/fib_armel 
Segmentation fault
rtc-draper commented 10 years ago

This bug was in the LDRi12 implementation (line 220), here: https://github.com/draperlaboratory/fracture/blob/master/lib/Target/ARM/ARMInvISelDAG.cpp#L220

LDRi12 has a valid pattern (see ARMGenInvISelDAG.cpp):

/*2079*/    OPC_CheckOpcode, TARGET_VAL(ARM::LDRi12),
/*2082*/    OPC_RecordNode,   // #0 = 'LDRi12' chained node
/*2083*/    OPC_MoveChild, 1,
/*2085*/    OPC_RecordNode,   // #1 = $base
/*2086*/    OPC_MoveParent,
/*2087*/    OPC_MoveChild, 2,
/*2089*/    OPC_RecordNode,   // #2 = $offsimm
/*2090*/    OPC_MoveParent,
/*2091*/    OPC_MoveChild, 3,
/*2093*/    OPC_RecordNode,   // #3 = $p
/*2094*/    OPC_MoveParent,
/*2095*/    OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectAddrModeImm12:$addr #4 #5
/*2098*/    OPC_EmitMergeInputChains1_0,
/*2099*/    OPC_EmitNode, TARGET_VAL(ISD::LOAD), 0|OPFL_Chain|OPFL_MemRefs,
                1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1,  // Results = #6
/*2107*/    OPC_CompleteMatch, 1, 0,

Sample instruction (the one causing the crash):

        %R3<def> = LDRi12 %R11, 4294967280, pred:14, pred:%noreg; mem:LD4[<unknown>](align=0) dbg::34012

Which works out to line 0x84DC:

000084DC:   10 30 1B E5                         ldr     r3, [r11, #-16]

Which gets translated too:

  %R11_7 = load i32* %R11, !dbg !126
  %R11_8 = add i32 %R11_7, -16, !dbg !126
  %R11_9 = inttoptr i32 %R11_8 to i32*, !dbg !126
  %R11_10 = load i32* %R11_9, !dbg !126
  store i32 %R11_10, i32* %R3, !dbg !126

Which loads from memory address r11-16 and stores it in r3 (looks right to me).

Please let me know why you thought you needed to implement it -- (maybe there's a test case where the Tablegen backend is failing!)

rtc-draper commented 10 years ago

See 910b5d2fe64ce5a5734b3364ef679053b57e5138 for fix.