Closed piranna closed 7 years ago
@piranna https://github.com/piranna thank you for your contribution. Are you using LEB128 somewhere in your project?
That's my intention, that's the only one Verilog implementation of LEB128 I've been able to find :-D My plan is to use to implement WebAssembly binary format on FPGA. You can find it at https://github.com/piranna/wasmachine
In unpack_i32.v https://github.com/drom/LEB128/pull/1#discussion_r104812754:
@@ -0,0 +1,56 @@ +module unpack_i32 (
- input [7:0] i0, i1, i2, i3, i4,
- output logic [31:0] o +);
- wire[31:0] u32_output;
- logic [4:0] gl, ub, ho, sb;
@piranna https://github.com/piranna I see that you are switching from always_comb -> always @* It might be good idea to completely switch to V2K and use reg/wire instead of logic. What do you think?
I'm fairly new to Verilog... I'm using Icarus Verilog, and it gave me an error when using always_comb, that's why I changed it. The same with logic, being this a pure combinational implementation, I find it a step back to use registers and delay the times, specially since I'm already using registers on my other components... From my understand I think they don't make sense here.
In Makefile https://github.com/drom/LEB128/pull/1#discussion_r104812965:
@@ -1,7 +1,7 @@ SRC = . BUILD = build
-IVERILOG = iverilog -I $(SRC)
@piranna https://github.com/piranna are you familiar with Verilator? I was thinking to use it to test the code.
No, could you point it to me? I was in fact looking for a tests units library for Verilog... At least Iearned some Makefile tricks :-P
In README.md https://github.com/drom/LEB128/pull/1#discussion_r104813408:
@@ -15,7 +16,7 @@ Encoding procedure. 0100110_0001110_1100101 shrink to a multiple of 7 bits 00100110 10001110 11100101 Add high 1 bits on all but last group to form bytes 0x26 0x8E 0xE5 HEX -0xE5 0x8E 0x26 Output byte stream +0xE5 0x8E 0x26 (0x00 0x00) Output byte stream
@piranna https://github.com/piranna what are these (0x00 0x00) mean?
Documentation, just to show where the not used bytes are located. I was geting crazy with that... Now it's clear that used bytes are i0, i1 and i2.
By the way, I was thinking to change the implementation to use generate and allow several widths, since I need unsigned 1, 7 and 32 bits and signed 7, 32 and 64 bits.
That would be a great idea :-)
El 8/3/2017 1:14 AM, "Aliaksei Chapyzhenka" notifications@github.com escribió:
I actually have LEB128 implemented in JavaScript here: https://github.com/drom/wasm-morph/blob/master/lib/leb128.js We can use it to generate more test cases to get better coverage.
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Sound interesting, but not sure if it's what we need here... Don't support testbed code, needed for the tests...
El 8/3/2017 6:31 PM, "Aliaksei Chapyzhenka" notifications@github.com escribió:
Here is https://www.veripool.org/wiki/verilator
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@piranna The trick with Verilator, is that you can write TestBench code in C/C++ or create NodeJS binding and write in JavaScript ;) Here is an example: https://github.com/drom/stack/tree/master/stack2
I actually have LEB128 implemented in JavaScript here: https://github.com/drom/wasm-morph/blob/master/lib/leb128.js We can use it to generate more test cases to get better coverage.