parametrize with template engine

[drom]

@piranna Verilog is not very good for configuring you modules. One simple (popular) way of dealing with the issue is to keep template of the design and generate multiple verilog files from it. In JS land we have ton of template engines like lodash.template for example. So we can keep something like this under GIT:

module unpack_${ obj.inputDataWidth }_${ obj.signed ? 'i' : 'u' }${ obj.outputDataWidth } (
    input  [${ obj.inputDataWidth - 1 } : 0] di,
    output [${  obj.outPutDataWidth - 1 } : 0] do
    ...
);

[piranna]

Using templates could be an option, but feels a bit hacky, not sure if we should give generate another try first... Until something is decided we could have versions for several widths.

[drom]

Verilog generate has very limited functionality and it is pretty useless for any sizable practical purpose. You can toy with it, but sooner or later you will need meta language on top of verilog.