Use combinational logic

[piranna]

Since the parallel implementation is mostly a rearrange of the bits, convert the modules to use combinational logic instead of behaviour one, so we don't need to use registers and can be able to produce the results on the fly, earning clock cycles and making it faster.

[drom]

@piranna Verilog is weird language. reg may mean combinatorial state if it is assigned inside combinatorial always @* block. In general if block has no clock signal, it takes 0 cycles.

[piranna]

That's strange, because I need to waste one cycle to give time to unpack to work... :-/

El 12/3/2017 18:31, "Aliaksei Chapyzhenka" notifications@github.com escribió:

Closed #5 https://github.com/drom/LEB128/issues/5.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub https://github.com/drom/LEB128/issues/5#event-996394940, or mute the thread https://github.com/notifications/unsubscribe-auth/AAgfvnyHtPkycyynjw_CpfRJONbg6QpLks5rlCvdgaJpZM4MahfL .

[drom]

@piranna you can add more calculations before and after unpack inside the same cycle.

[piranna]

Yes, I know, it's more related about how to wait until they have finished to do other things... Until now I'm only able to do async asignations, no more :-/ Not sure if by serendipity this will have some advantages later if we move to a pipelined architecture, though...

El 13/3/2017 1:19, "Aliaksei Chapyzhenka" notifications@github.com escribió:

@piranna https://github.com/piranna you can add more calculations before and after unpack inside the same cycle.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub https://github.com/drom/LEB128/issues/5#issuecomment-285990135, or mute the thread https://github.com/notifications/unsubscribe-auth/AAgfviEGOPJnnDdFptADJOrfYb4H9DcYks5rlIt2gaJpZM4MahfL .