Closed piranna closed 7 years ago
@piranna Verilog is weird language. reg
may mean combinatorial state if it is assigned inside combinatorial always @*
block. In general if block has no clock
signal, it takes 0 cycles.
That's strange, because I need to waste one cycle to give time to unpack to work... :-/
El 12/3/2017 18:31, "Aliaksei Chapyzhenka" notifications@github.com escribió:
Closed #5 https://github.com/drom/LEB128/issues/5.
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@piranna you can add more calculations before and after unpack inside the same cycle.
Yes, I know, it's more related about how to wait until they have finished to do other things... Until now I'm only able to do async asignations, no more :-/ Not sure if by serendipity this will have some advantages later if we move to a pipelined architecture, though...
El 13/3/2017 1:19, "Aliaksei Chapyzhenka" notifications@github.com escribió:
@piranna https://github.com/piranna you can add more calculations before and after unpack inside the same cycle.
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Since the parallel implementation is mostly a rearrange of the bits, convert the modules to use combinational logic instead of behaviour one, so we don't need to use registers and can be able to produce the results on the fly, earning clock cycles and making it faster.