dspsandbox / Canvas

Graphical environment for Digital Signal Processing
MIT License
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paramiko ssh_exception #2

Closed pdibartolomeo closed 2 years ago

pdibartolomeo commented 3 years ago

Hi, on ubuntu 18.04 main.py raises an ecxception when doing VERIFY on the FPGA. It turned out that modifying self.ssh.connect(IP, port=PORT, username=USER, password=PWD) into self.ssh.connect(IP, port=PORT, username=USER, password=PWD, allow_agent=False) worked.

dspsandbox commented 3 years ago

Thanks for reporting this issue. I have updated the code according to your suggestion, please let me know if you still encounter problems on your Ubuntu system. Best regards!

david-mcginnis commented 2 years ago

I have been trying the x32_delayVariable block with no success. I have been able to run a bunch of different projects with no problem but when I try to use the x32_delayVariable, the Vivado server returns and error.

Status SYNTH/IMPL ERROR Please check .log files (Zynq_7010 directory).

Except the Zynq_7010 directory is not created. I made a very simple project that has an ADC into the delay block with a DAC out of the delay block along with the required constants. Here is the NET_parsed.net output:

x32_dac1_0 N000 x32_dac1 x32_delayVariable_0 N001 N002 N003 N000 x32_delayVariable x32_adc1_0 N001 x32_adc1 x32_const_0 N002 x32_const x1_const_0 N003 x1_const

dspsandbox commented 2 years ago

Hello, based on the provided netlist there seems to be a disconnected x32_delayVariable in your design. Have you tried to start the same design from scratch (i.e. creating a new LtSpice project)? If the problem persists, please share the LtSpice file amd I will further investigate the issue. Cheers, Pau

david-mcginnis commented 2 years ago

I have tried a completely new project with the same results. I am enclosing the LTSpice file. Dav mainCircuit.asc.txt e

dspsandbox commented 2 years ago

Hi Dave, thanks for sharing your design. It helped me to find a bug in the source code of the x32_delayVariable module. The bug got resolved and your design now goes through synthesis/implementation without errors. Best regards, Pau

david-mcginnis commented 2 years ago

Hi Pau,

I tried it. It works! Fantastic!

Dave