Adc dac

[fabzz60]

Hello I test the echo analog programm but I want to Connect only ADC directly on DAC. It’s not working .I have Vivado 2019.1 I have make the same design on the demo écho analog. Thanks for your reply Cordially Fabzz60

[dspsandbox]

Hi there, hmm that is strange... Where you able to run the analog echo design as it is defined in the tutorial? Is the led blink working? Cheers, Pau

[fabzz60]

Hello,

I have not tested the demo led because I have already used sdk and made some simple projects under vivado and sdk. I have been working on the redpitaya for a short time and with students. the objective is to use adc and dac to achieve synchronous demodulation and PID... for the echo analog demo, I just didn't set the IP offsets and send the adc signals directly to the dacs. I will redo a new project and make exactly your demo echo analog thank you for returning

fabzz60 Envoyé de mon iPhone

Envoyé de mon iPhone Le 26 mai 2022 à 16:38, Pau Gómez @.***> a écrit :



Hi there, hmm that is strange... Where you able to run the analog echo design as it is defined in the tutorial? Is the led blink working? Cheers, Pau

— Reply to this email directly, view it on GitHubhttps://github.com/dspsandbox/FPGA-Notes-for-Scientists/issues/5#issuecomment-1138649574, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AX6GU7DCYJSPSQZNLQWTV5TVL6EHZANCNFSM5XBHDG6Q. You are receiving this because you authored the thread.Message ID: @.***>

[david-mcginnis]

I am problems with the Analog_echo tutorial. I have successfully run the LED tutorials. However, there is a problem with the redpitaya_125_14_clk IP. The problem starts at synthesis and I am enclosing some screen shots.

[fabzz60]

Hello,

My analog echo is working. I modified it for my project.

The problem I had was that I had bought red pitaya 125-14 external clocks and two of them were already pre-wired to receive an external clock on the extension connector pins!!!

Only one of the three red pitaya cards I purchased was wired standard. So I had no @.*** signal on the ADC which transmits the clock signal to the Zynq then to the DAC.

I had to modify the hardware to start my project, put two resistors of 22 ohms R25, R26 in place as on the initial diagram of the Red pitaya V1.0.

It's a bad joke from the manufacturer no doubt!!! Attached is the screenshot of the tutorial that I modified for my project. The IP clk module gave me no problems. Fabzz60 (France CNRS)

On the other hand, I specify that I program the Zynq (PS and PL FPGA part) with a USB-JTAG HS2 Digilent cable and I use the Analog Discovery 2 digital scope.

[image: ff412707-8e98-4c56-8286-67a5a92067ec.jpg]

[image: f43f73a7-9328-44ce-81a0-b71fe80d162d.jpg]

Wiotte Fabrice - Ingénieur CNRS Laboratoire de Physique des Lasers Institut Galilée Bât D Université Sorbonne Paris Nord, Sorbonne Paris Cité 99 av. Jean-Baptiste Clément 93430 Villetaneuse Tél : 01 49 40 33 94

http://www-lpl.univ-paris13.fr/ Réseau des électroniciens du CNRS: page Wiki Le groupe DDS https://wiki.electroniciens.cnrs.fr/index.php/Le_groupe_DDS https://wiki.electroniciens.cnrs.fr/index.php/Le_groupe_DDS GitHub_projects https://github.com/fabzz60/ https://github.com/fabzz60/

Le mer. 1 juin 2022 à 08:08, David McGinnis @.***> a écrit :

I am problems with the Analog_echo tutorial. I have successfully run the LED tutorials. However, there is a problem with the redpitaya_125_14_clk IP. The problem starts at synthesis and I am enclosing some screen shots.

[image: analog_echo_synth_tcl] https://user-images.githubusercontent.com/17161951/171338746-8cae357a-5bab-4695-bb79-7df034caa616.png [image: analog_echo_synth_message] https://user-images.githubusercontent.com/17161951/171338751-42ab536d-d480-4767-a718-d503788df5f9.png [image: analog_echo_diagram] https://user-images.githubusercontent.com/17161951/171338753-f94357fa-1205-4d72-b817-bad315f56249.png

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[david-mcginnis]

My issue starts with the synthesis part which is well before I get to the hardware. I am using Vivado HLx webpack 2020.2 on a 18.04.6 LTS Ubuntu desktop. Did you get the tutorial to work following the steps?

[dspsandbox]

Hi @david-mcginnis,

I have just verified the analog echo on a fresh install of Vivado 2020.2 Webpack on Ubuntu 20.04.4 LTS without any errors. What you are describing seems like a problem related to the IP source files. Are you using the latest version of this repo?

BR, Pau

[david-mcginnis]

I just did a git pull and it said that I am up to date. I am using commit commit 92f0571a189c869f9fbb7b848e77fbdd2afe3e74. I used the default choices when using the Xilinx unified installer - see picture

[dspsandbox]

Yes, these installation settings are correct. I assume you have already tried to run the example after reinstalling Vivado, downloading again the repo (or even do all that in a new Ubuntu 20.04 LTS virtual machine)? I know that these steps are annoying/lengthy but this is the securest option to get a clean development environment.

[david-mcginnis]

It's working! I believe the problem was that I did not follow your instructions in the tutorial to un-comment the following lines in redpitaya-125-14.xdc

8,9,28,47,52,59,60,81,180

I thought these lines were suppose to be comments because they had more than one '#' symbol. When I un-commented these lines, everything worked - is this correct or just a coincidence?

[fabzz60]

Hello, Great! Good evening

Envoyé de mon iPhone

Le 1 juin 2022 à 20:15, David McGinnis @.***> a écrit :

 It's working! I believe the problem was that I did not follow your instructions in the tutorial to un-comment the following lines in redpitaya-125-14.xdc

8,9,28,47,52,59,60,81,180

I thought these lines were suppose to be comments because they had more than one '#' symbol. When I un-commented these lines, everything worked - is this correct or just a coincidence?

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[dspsandbox]

These lines are indeed comments and should always have at least one # in front. Is it possible that the errors you got before are because you left the lines below 180 commented out? In other words, if the lines below 180 are commented out the input clock frequency remains undefined and this could lead to a problems when synthesizing the MMCM/PLL within the clock IP. Just a guess...

[david-mcginnis]

I put the comment symbol back on these lines, refreshed the hierarchy and re-ran the synthesis, implementation, and generated the bitstream and it worked. So it is working as intended.

Question: should the ports we add be of type "Other" ?

[dspsandbox]

Yes, using type "other" is fine. In principle, there is no need to use the "clock" type (which includes a frequency attribute) since we use the .xdc file to define the clock frequencies