Update diff April 12th 2024, 4:41:43 pm - Githubissues

dtcxzyw / llvm-opt-benchmark

An LLVM IR dataset for data-driven compiler optimization research

https://dtcxzyw.github.io/llvm-opt-benchmark/

MIT License

18 stars 5 forks source link

Update diff April 12th 2024, 4:41:43 pm #510

Open github-actions[bot] opened 5 months ago

github-actions[bot] commented 5 months ago

from: https://github.com/llvm/llvm-project/commit/5752e3196bc52fdac70e3650abc703570ff6209b to: https://github.com/llvm/llvm-project/commit/8d468c132eed7ffe34d601b224220efd51655eb3 commit: fbeb177b2b11c6648129a9dbe02ecaf43b709044

Change Logs

from 5752e3196bc52fdac70e3650abc703570ff6209b to 8d468c132eed7ffe34d601b224220efd51655eb3

8d468c132eed7ffe34d601b224220efd51655eb3 NFC: Make clang resource headers an interface library (#88317) b794dc23255505dd7735f995b8ff1192305a072e [SystemZ] Add custom handling of legal vectors with reduce-add. (#88495) b614e5b0340f783ad355899248c52cb22a04b014 [SystemZ] Add missing (dis-)assembly tests. (#88498) 6f1e23b47d428d792866993ed26f4173d479d43d [MLIR][Bufferization] Choose default memory space in tensor copy insertion (#88500) e0a628715a8464e220c8ba9e9aaaf2561139198a [ValueTracking] Convert isKnownNonZero to use SimplifyQuery (#85863) 72dfee114bd38dc4b424d392bc14cd6b7dfb79e5 [RISCV] Remove mayLoad = 1 from store-conditional (#88470) 040efafa9fef101924d3cf67db20f6429ce1c871 [RISCV] Support uimm32 immediates in RISCVInstrInfo::movImm for RV32. (#88464) 4dd20b0728223ff20f4817edc2f89901385cb990 [BOLT][NFC] Refactor relocation loop (#88424)

dtcxzyw commented 5 months ago

https://github.com/dtcxzyw/llvm-opt-benchmark/pull/429#discussion_r1533983799

dtcxzyw commented 5 months ago

It has been handled by CVP, but not by InstCombine.