rust-embedded/riscv (riscv-rt)
### [`v0.12.0`](https://redirect.github.com/rust-embedded/riscv/releases/tag/v0.12.0): `riscv` 0.12.0
### New features
#### `riscv` 0.12.0
- Support for target-dependent external interrupt and exception numbers
- `riscv-macros` for helping during the definition of custom interrupt and exception sources
- Macros for automating the definition of new CSRs
#### `riscv-pac` 0.2.0
- Enumeration of common errors for RISC-V targets at the register level
- All PAC traits now work with `usize` numbers
- New `ExceptionNumber` trait for custom exception numbers
#### `riscv-peripheral` 0.2.0
- Adapt to new changes in the RISC-V ecosystem
#### `riscv-rt` 0.13.0
- Now exceptions rely on the `_dispatch_exception` function
- Now interrupts rely on the `_dispatch_interrupt` function
- While the crate provides a default implementation for the previously mentioned functions, you can skip these functions with the new `no-exceptions` and `no-interrupts` features. This way, you can adapt `riscv-rt` to target-specific sources.
- New `pre_init_trap` to detect early errors during the boot process.
- Vectored interrupts handling is now available under the `v-trap` feature!
- New `core_interrupt`, `external_interrupt`, and `exception` macros for defining interrupt and exception handlers
- New `u-boot` feature to execute U-boot binaries.
### [`v0.10.0`](https://redirect.github.com/rust-embedded/riscv/compare/v0.9.0...v0.10.0)
[Compare Source](https://redirect.github.com/rust-embedded/riscv/compare/v0.9.0...v0.10.0)
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♻ Rebasing: Whenever PR becomes conflicted, or you tick the rebase/retry checkbox.
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This PR contains the following updates:
0.9.0->0.13.0Release Notes
rust-embedded/riscv (riscv-rt)
### [`v0.12.0`](https://redirect.github.com/rust-embedded/riscv/releases/tag/v0.12.0): `riscv` 0.12.0 ### New features #### `riscv` 0.12.0 - Support for target-dependent external interrupt and exception numbers - `riscv-macros` for helping during the definition of custom interrupt and exception sources - Macros for automating the definition of new CSRs #### `riscv-pac` 0.2.0 - Enumeration of common errors for RISC-V targets at the register level - All PAC traits now work with `usize` numbers - New `ExceptionNumber` trait for custom exception numbers #### `riscv-peripheral` 0.2.0 - Adapt to new changes in the RISC-V ecosystem #### `riscv-rt` 0.13.0 - Now exceptions rely on the `_dispatch_exception` function - Now interrupts rely on the `_dispatch_interrupt` function - While the crate provides a default implementation for the previously mentioned functions, you can skip these functions with the new `no-exceptions` and `no-interrupts` features. This way, you can adapt `riscv-rt` to target-specific sources. - New `pre_init_trap` to detect early errors during the boot process. - Vectored interrupts handling is now available under the `v-trap` feature! - New `core_interrupt`, `external_interrupt`, and `exception` macros for defining interrupt and exception handlers - New `u-boot` feature to execute U-boot binaries. ### [`v0.10.0`](https://redirect.github.com/rust-embedded/riscv/compare/v0.9.0...v0.10.0) [Compare Source](https://redirect.github.com/rust-embedded/riscv/compare/v0.9.0...v0.10.0)Configuration
📅 Schedule: Branch creation - At any time (no schedule defined), Automerge - At any time (no schedule defined).
🚦 Automerge: Disabled by config. Please merge this manually once you are satisfied.
♻ Rebasing: Whenever PR becomes conflicted, or you tick the rebase/retry checkbox.
🔕 Ignore: Close this PR and you won't be reminded about this update again.
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