dwarning / VA-Models

Verilog-A simulation models
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bsim4 again #6

Closed felix-salfelder closed 10 months ago

felix-salfelder commented 10 months ago

During refactoring, the default for ni0sub has changed from 1.45e10 to 1.45e16. I wonder if this was intentional. Further down, in code conditional on mtrlmod==0, the constant 1.45e10 is still used in ni. I had a cursory look at the original model, and it looks like 10 there as well.

Within the five contribution statements I(..) <+ BSIM4type * ddt(..), replacing BSIM4type by just type will simplify optimisation: both are supposedly constant, but BSIM4type is harder to tell. Generally, perhaps it will be better to get rid of all/most BSIM4* variables in favour of actual (local)param constants?

Related, the @(initial_step) event kludge looks wrong, and appears to make things worse. Perhaps it should be made conditional, as in

   `ifdef insideADMS
     `define INITIAL_INSTANCE @(initial_instance)
   `elsif __SOME_SOFTWARE__
     `define INITIAL_INSTANCE @(initial_step)
   `else
      `define INITIAL_INSTANCE
   `endif

Thanks felix

dwarning commented 10 months ago

Hi Felix, Thanks for your hints. The entire bsim4 code is a kludge and should act more as a placeholder. But you are right, the ni0sub parameter is wrong with e+16. I thing the author of the va code take over the wrong value from pdf manual 4.8.0. Any 4.8 C code has e+10. BTW: You have a model with mtrlmod=1 parameter for new materials? Anyway - I will change. I agree to get rid the the BSIM4* = variable assignment block but want not spent so much effort because the model is build-in in most simulators. Is it worth in your opinion? OpenVAF has his own rules for ordering the variable initialization and don't need the pseudo events. I will change the code.

felix-salfelder commented 10 months ago

On Wed, Nov 29, 2023 at 07:46:35AM -0800, dwarning wrote:

The entire bsim4 code is a kludge and should act more as a placeholder. I agree to get rid the the BSIM4* = variable assignment block but want not spent so much effort because the model is build-in in most simulators. Is it worth in your opinion?

I only use bsim4 for testing.

It seems that vamodel + paramset is superior to the Berkeley C code, for reasons discussed elsewhere. This could be a reason to maintain bsim4.va and move forward to an idiomatic implementation. Of course, there's still an issue with the license, so let's keep it educational...

OpenVAF has his own rules for ordering the variable initialization and don't need the pseudo events. I will change the code.

I have not checked OpenVAF for corner-case behaviour involving initial_step. Im curious if it works according to standard.

For full Verilog-AMS, we need the non-pseudo events anyway. I might revisit optimisations involving event-dependent values at a later stage, but there's tons of lower hanging fruit.

thanks felix

dwarning commented 10 months ago

Fixed by commit.