dz333 / secverilog

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Create path assignment analysis #9

Closed dz333 closed 1 year ago

dz333 commented 1 year ago

Create a new static analysis (add this in a new file, don't just add it all into typecheck.cc).

This analysis should, for each "sequential" variable v, return a set of path expressions which represents all of the paths under which v is assigned.

For example, in the following program:

reg [1:0] x,y,z,zz;
always@(posedge clk) begin
    x <= 2;
    if (a) begin
        y <= 3;
    end
    if (b) begin
        z <= 1;
    end else begin
        z <= 0;
        y <= 0;
    end
end

The analysis should return the following information: [ x -> { true }; y -> { a, !b }; z -> { b, !b }; zz -> { } ]


Arrays

This analysis should treat each array access expression as a separate variable. Currently, we only reason about index expressions that are variables or constants; this could be extended in the future.

For example:

reg arr [3:0];
always@(posedge clk) begin
    arr[x] <= 1;
    if (a) begin
        arr[y] <= 0;
    end else begin
        arr[z] <= 1;
    end
end

The analysis should return: [ arr[x] -> { true }; arr[y] -> { a }, arr[z] -> { !a } ]

dz333 commented 1 year ago

This is a sub-part of issue #8

charles-rs commented 1 year ago

done?