osbornjd
commented
2 years ago line 20 - the "benefits of near real-time analysis" begs for a reference.
Added two LHCb Turbo references.
line 28 - experiments -> facilities (the EIC is a facility not an experiment)
Modified as suggested.
line 32 - the Computing Plan -> this computing plan.
Modified as suggested.
line 52 : readout -> "read out" or better "collected"
Modified to collected.
lines 62-64 : the sections assumes complete familiarity the ATLAS FELIX cards, and does not define or even attribute the term FELIX. This should be expanded into a new paragraph that says we are considering PCIe-based received cards similar to the FELIX card being used by the ATLAS detector (reference) and some brief details. It might be nice to distinguish the FELIX card (which exists) from what we plan to build by calling the latter EIC-FELIX in the subsequent text.
We added the following, in addition to a citation to Chen:2019owc:
"FELIX is designed for new or upgraded detectors and trigger systems in the ATLAS Phase-I upgrade and High-Luminosity LHC, and is implemented by server PCs with commodity network interfaces and PCIe cards with large field-programmable gate arrays (FPGAs) and many high speed serial fiber transceivers. "
line 131 : "allow to input" -> accept as input
Changed as suggested.
line 153 : increasing -> increase
Changed as suggested.
line 173 : the term "FST" has not been defined
Changed to forward silicon detectors.
line 180: We do not anticipate such a bottleneck for ECCE. (In sPHENIX this is a limitation of the DCM-II modules.)
You're right, there will be no bottleneck so this part is confusing. For the current work, we're not focusing on the calorimeters so we removed lines 176 - 181
lines 226-228: An analysis purely based on port rates and data volumes assumes an efficiency in packaging the data that never occurs in real life. It will also be important to balance the data rates by underpopulating the FELIX cards in high-data systems. In the DAQ/Electronics analysis note I think we came to of order 120 FELIX cards.
We cross checked with Martin and Jan on the reasoning here and it boils down to needing to meet certain I/O rates (e.g. we had only discussed in and not out). There is also some flexibility in what generation PCIe is used, which is expected to of course improve in the next 10 years. Based on their comments we added a "catch all": "...A current-generation FELIX card has ports that support 48 fibers, leading to $\mathcal{O}$(20) FELIX cards. Non-optimal distribution of FEE bandwidth across the fibers, the uncertainty in achievable reduction rate in the FELIX and achievable out-bound bandwidth may grow the number of required FELIX cards up to 3 fold for a total of 60."
Figure 2 caption - left->top, right->bottom
Modified as suggested.
line 553: The second simulation campaign featured a far more mature detector design....
Modified as suggested.
line 792 - don't forget to add the appropriate Acknowledgements, including the labs and the DOE.
Sure. Will we have a default acknowledgment blurb we copy in or should we write one ourself, specific to the authors of the paper?
Congratulations to the ECCE computing team on preparing such a thorough an comprehensive note. I have just a few comments, most of them minor:
line 20 - the "benefits of near real-time analysis" begs for a reference.
line 28 - experiments -> facilities (the EIC is a facility not an experiment)
line 32 - the Computing Plan -> this computing plan.
line 52 : readout -> "read out" or better "collected"
lines 62-64 : the sections assumes complete familiarity the ATLAS FELIX cards, and does not define or even attribute the term FELIX. This should be expanded into a new paragraph that says we are considering PCIe-based received cards similar to the FELIX card being used by the ATLAS detector (reference) and some brief details. It might be nice to distinguish the FELIX card (which exists) from what we plan to build by calling the latter EIC-FELIX in the subsequent text.
line 131 : "allow to input" -> accept as input
line 153 : increasing -> increase
line 173 : the term "FST" has not been defined
line 180: We do not anticipate such a bottleneck for ECCE. (In sPHENIX this is a limitation of the DCM-II modules.)
lines 226-228: An analysis purely based on port rates and data volumes assumes an efficiency in packaging the data that never occurs in real life. It will also be important to balance the data rates by underpopulating the FELIX cards in high-data systems. In the DAQ/Electronics analysis note I think we came to of order 120 FELIX cards.
Figure 2 caption - left->top, right->bottom
line 553: The second simulation campaign featured a far more mature detector design....
line 792 - don't forget to add the appropriate Acknowledgements, including the labs and the DOE.