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echopen / PRJ-medtech_embsys

Master repository for development targeting the embedded Platform
BSD 3-Clause "New" or "Revised" License
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UART receiver and transmitter IP #2

Open eiffel-fl opened 7 years ago

eiffel-fl commented 7 years ago

The goal is to develop two IPs for UART :

Indicative deadline : 15~30 may

sprotch commented 7 years ago

What is the goal here? To implement UART controllers in VHDL for the programmable logic part of the RedPitaya? Why do we not use the HW controllers in the Zynq PS?

eiffel-fl commented 7 years ago

The goal is to implement UART in Verilog to permit this card to send and receive data from the PC it is connected.

sprotch commented 7 years ago

A full reference design for a 16550 UART on Lattice ICE40 already exists: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/ReferenceDesigns/ReferenceDesigns01/UART16550Transceiver.aspx If you don't want to go with this design, have a look at OpenCores (opencores.org). Several open source cores already exist. And if none of the above fits your needs, I would advise to go with a single core/IP and not two separate ones (one for TX and the other for TX) to make synchronization easier and implement a real UART in a single module.

eiffel-fl commented 7 years ago

I know about opencores.org and I check some design but I want to design mine.

I will try to make only one IP if you think that it is better.

eiffel-fl commented 7 years ago

I am encountering problem with the tool to synthesize the TX IP. When I test the code which is synthesized in my testbench it seems that the state registers are 'X' which seems impossible.

I will investigate this but as I am in holiday next week I will not be able to finish for the 30th May, so the new indicative date will be 15th-30th June.

sprotch commented 7 years ago

Do you have your code committed somewhere so that others can review and perhaps help to find the issue?

eiffel-fl commented 7 years ago

Yes here .

I reviewed it and I did not find something aberrant. I think I will change the design of the TX IP hoping it will help.