Design the verilog code for signal processing

echopen / PRJ-medtech_embsys

Master repository for development targeting the embedded Platform

BSD 3-Clause "New" or "Revised" License

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Design the verilog code for signal processing #5

Open halipster opened 7 years ago

halipster commented 7 years ago

Implement all the necessary verilog blocks in order to achieve the digital signal processing in the FPGA as :

denoising
demodulation
decimation

halipster commented 7 years ago

I already wrote a block for IQ demodulation and for sqrt computing. I'm working on the denoising part as it will be just a FIR filter which will be very similar to the demodulation block.