how do I start the svd viewer?

soundart commented 8 months ago

Hi,

sorry for the question :) I have not used cortex-debug before and I am not sure what to expect.

I am trying to connect to a qemu like system and see the registers of one of the uarts.

What I did:

created launch.json looks like:

 {
            "name": "Qemu Attach with GDB",
            "type": "cppdbg",
            "request": "launch",
            "program": "${workspaceFolder}/build/debug/sw/arm64/linux/vmlinux-4.19.4",
            "MIMode": "gdb",
            "miDebuggerPath": "/usr/bin/gdb-multiarch",
            "miDebuggerServerAddress": "localhost:1234",
            "cwd": "${workspaceFolder}/build/debug/sw/arm64/linux/linux-4.19.4",
            //"useExtendedRemote": true,
            "svdPath": "${workspaceFolder}/vscode/svd/arm_uart_pl011.svd",
            "logging": { "engineLogging": true, "trace": true, "traceResponse": true },
   }

I merged various snippets of svd files together and have now the code below. The cpu part is a lie, the system has a different CPU (Cortex A72) and GIC (GIC400), but I do not now if these parts are relevant for now.

<?xml version="1.0" encoding="UTF-8"?>
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
  <vendor>soundart</vendor>
  <name>arm_uart_pl011</name>
  <version>1.0</version>
  <description>SYS64</description>
  <licenseText></licenseText>
  <cpu>
    <name>CM7</name>
    <revision>r0p1</revision>
    <endian>little</endian>
    <mpuPresent>true</mpuPresent>
    <fpuPresent>true</fpuPresent>
    <vtorPresent>true</vtorPresent>
    <nvicPrioBits>4</nvicPrioBits>
    <vendorSystickConfig>false</vendorSystickConfig>
  </cpu>
  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->
  <width>32</width>                                               <!-- bus width is 32 bits -->
  <!-- default settings implicitly inherited by subsequent sections -->
  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals
                                                                       and register that do not define "size" themselves -->
  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->
  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->
  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->
  <peripherals>
  <peripheral>
      <name>uart01</name>
      <description>ARM Prime Cell PL011</description>
      <baseAddress>0x10009000</baseAddress>
      <headerStructName>ARM_UART_PL011</headerStructName>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x8</size>
        <usage>registers</usage>
      </addressBlock>
      <addressBlock>
        <offset>0x8</offset>
        <size>0x10</size>
        <usage>reserved</usage>
      </addressBlock>
      <addressBlock>
        <offset>0x18</offset>
        <size>0x4</size>
        <usage>registers</usage>
      </addressBlock>
      <addressBlock>
        <offset>0x1c</offset>
        <size>0x4</size>
        <usage>reserved</usage>
      </addressBlock>
      <addressBlock>
        <offset>0x20</offset>
        <size>0x2c</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>DR</name>
          <description>Data Register</description>
          <addressOffset>0x0000</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>DATA</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FE</name>
              <description>FE</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PE</name>
              <description>PE</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BE</name>
              <description>BE</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OE</name>
              <description>OE</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RSR</name>
          <description>Receive Status Register</description>
          <addressOffset>0x0004</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>FE</name>
              <description>FE</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PE</name>
              <description>PE</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BE</name>
              <description>BE</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OE</name>
              <description>OE</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ECR</name>
          <description>Error Clear Register</description>
          <addressOffset>0x0004</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>FE</name>
              <description>FE</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>PE</name>
              <description>PE</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>BE</name>
              <description>BE</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OE</name>
              <description>OE</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FR</name>
          <description>Flag Register</description>
          <addressOffset>0x0018</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>CTS</name>
              <description>CTS</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DSR</name>
              <description>DSR</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DCD</name>
              <description>DCD</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUSY</name>
              <description>BUSY</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXFE</name>
              <description>RXFE</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXFF</name>
              <description>TXFF</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXFF</name>
              <description>RXFF</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXFE</name>
              <description>TXFE</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RI</name>
              <description>RI</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IBRD</name>
          <description>Integer Baud Rate Register</description>
          <addressOffset>0x0024</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>BAUDDIVINT</name>
              <description>BAUDDIVINT</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FBRD</name>
          <description>Fractional Baud Rate Register</description>
          <addressOffset>0x0028</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>BAUDDIVFRAC</name>
              <description>BAUDDIVFRAC</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LCR_H</name>
          <description>Line Control Register</description>
          <addressOffset>0x002C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>BRK</name>
              <description>BRK</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PEN</name>
              <description>PEN</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EPS</name>
              <description>EPS</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>STP2</name>
              <description>STP2</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FEN</name>
              <description>FEN</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WLEN</name>
              <description>WLEN</description>
              <bitOffset>5</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPS</name>
              <description>SPS</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CR</name>
          <description>Control Register</description>
          <addressOffset>0x0030</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>UARTEN</name>
              <description>UARTEN</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SIREN</name>
              <description>SIREN</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SIRLP</name>
              <description>SIRLP</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXE</name>
              <description>TXE</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXE</name>
              <description>RXE</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DTR</name>
              <description>DTR</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RTS</name>
              <description>RTS</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RTSEN</name>
              <description>RTSEN</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CTSEN</name>
              <description>CTSEN</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IFLS</name>
          <description>Interrupt FIFO Level Select Register</description>
          <addressOffset>0x0034</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>TXIFLSEL</name>
              <description>TXIFLSEL</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXIFLSEL</name>
              <description>RXIFLSEL</description>
              <bitOffset>3</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IMSC</name>
          <description>Interrupt Mask set_Clear Register</description>
          <addressOffset>0x0038</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>RIMIM</name>
              <description>RIMIM</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CTSMIM</name>
              <description>CTSMIM</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DCDMIM</name>
              <description>DCDMIM</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DSRMIM</name>
              <description>DSRMIM</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXIM</name>
              <description>RXIM</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXIM</name>
              <description>TXIM</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RTIM</name>
              <description>RTIM</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FEIM</name>
              <description>FEIM</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PEIM</name>
              <description>PEIM</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BEIM</name>
              <description>BEIM</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OEIM</name>
              <description>OEIM</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RIS</name>
          <description>Raw Interrupt Status Register</description>
          <addressOffset>0x003C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x0</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>RIRMIS</name>
              <description>RIRMIS</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CTSRMIS</name>
              <description>CTSRMIS</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DCDRMIS</name>
              <description>DCDRMIS</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DSRRMIS</name>
              <description>DSRRMIS</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXRIS</name>
              <description>RXRIS</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXRIS</name>
              <description>TXRIS</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RTRIS</name>
              <description>RTRIS</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FERIS</name>
              <description>FERIS</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PERIS</name>
              <description>PERIS</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BERIS</name>
              <description>BERIS</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OERIS</name>
              <description>OERIS</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MIS</name>
          <description>Masked Interrupt Status Register</description>
          <addressOffset>0x0040</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x0</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>RIMMIS</name>
              <description>RIMMIS</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CTSMMIS</name>
              <description>CTSMMIS</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DCDMMIS</name>
              <description>DCDMMIS</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DSRMMIS</name>
              <description>DSRMMIS</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXMIS</name>
              <description>RXMIS</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXMIS</name>
              <description>TXMIS</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RTMIS</name>
              <description>RTMIS</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FEMIS</name>
              <description>FEMIS</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PEMIS</name>
              <description>PEMIS</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BEMIS</name>
              <description>BEMIS</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OEMIS</name>
              <description>OEMIS</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ICR</name>
          <description>Interrupt Clear Register</description>
          <addressOffset>0x0044</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>RIMIC</name>
              <description>RIMIC</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CTSMIC</name>
              <description>CTSMIC</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DCDMIC</name>
              <description>DCDMIC</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DSRMIC</name>
              <description>DSRMIC</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>RXIC</name>
              <description>RXIC</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TXIC</name>
              <description>TXIC</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>RTIC</name>
              <description>RTIC</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>FEIC</name>
              <description>FEIC</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>PEIC</name>
              <description>PEIC</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>BEIC</name>
              <description>BEIC</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OEIC</name>
              <description>OEIC</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMACR</name>
          <description>DMA Control Register</description>
          <addressOffset>0x0048</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <resetMask>0xffffffff</resetMask>
          <fields>
            <field>
              <name>RXDMAE</name>
              <description>RXDMAE</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXDMAE</name>
              <description>TXDMAE</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DMAONERR</name>
              <description>DMAONERR</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
  </peripherals>
</device>

It validates using svdconv --strict

If I connect to the system I can stop the qemu CPU and see the stack trace. I would expect to see the peripheral view now, but nothing happens. Where do I have to look or launch it?

thegecko commented 8 months ago

Hi @soundart

There's a few things to check here....

I have not used cortex-debug before

Your launch.json config outlines you are using the cppdbg debugger which is from the cpptools extension, not cortex-debug extension.

Which device are you trying to debug and which debugger do you want to use?

svdPath": "${workspaceFolder}/vscode/svd/arm_uart_pl011.svd",

svdPath has recently been renamed to definitionPath, can you also check the path, as the .vscode folder has a dot in it.

This extension is standalone and should appear when the following conditions are met:

A debug session is started
Valid data is loaded from the svd file

You can check the latter by loading any valid svd file, e.g.:

{
           "name": "Qemu Attach with GDB",
           "type": "cppdbg",
           "request": "launch",
...
           "definitionPath": "https://pack-content.cmsis.io/NXP/K32L3A60_DFP/18.0.0/devices/K32L3A60/K32L3A60_cm4.xml",
...
  }

Please let us know if you still fail to see the peripheral window after trying this.

soundart commented 8 months ago

On 2/18/24 13:15, Rob Moran wrote:

Hi @soundart https://github.com/soundart

Hi @thegecko!

There's a few things to check here....
I have not used cortex-debug before
Your launch.json config outlines you are using the |cppdbg| debugger which is from the cpptools extension https://marketplace.visualstudio.com/items?itemName=ms-vscode.cpptools, not cortex-debug extension https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug.

Yes this is correct. I wanted to say, that I do not know what to expect from user-experience point of view.

Which device are you trying to debug and which debugger do you want to use?

The device is a virtual device emulated by qemu. As a debugger I want to use /usr/bin/gdb-multiarch. On the visual studio side I want to use "cppdbg".

This works so far: I can see sources and step in the linux kernel.

svdPath": "${workspaceFolder}/vscode/svd/arm_uart_pl011.svd",
|svdPath| has recently been renamed to |definitionPath|, can you also check the path, as the |.vscode| folder has a dot in it.

I stored the svd in a path without a dot.

$ file vscode/svd/arm_uart_pl011.svd vscode/svd/arm_uart_pl011.svd: XML 1.0 document, ASCII text

Nothing changes if I move it inside the .vscode folder and adapt the lauch.json

This extension is standalone and should appear when the following conditions are met:

A debug session is started

Valid data is loaded from the svd file

You can check the latter by loading any valid svd file, e.g.:

{ "name":"Qemu Attach with GDB", "type":"cppdbg", "request":"launch", ... "definitionPath":"https://pack-content.cmsis.io/NXP/K32L3A60_DFP/18.0.0/devices/K32L3A60/K32L3A60_cm4.xml", ... }

I have SVD Viewer v1.2.3 and a red "preview" label attached to it. I see no button to upgrade further.

If I am changing svdPath to definitionPath, then launch.json reports a problem: "Property definitionPath is not allowed."

Please let us know if you still fail to see the peripheral window after trying this.

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thegecko commented 8 months ago

OK, I can see your confusion, which is my fault, sorry!

I assume you are using cortex-debug.svd-viewer? This is being deprecated in favour of clipse-cdt.peripheral-inspector (this repository).

Could you use the new extension, then try the definitionPath test above (pointing at the svd file url) to see if anything appears for you at all?

soundart commented 8 months ago

Hi,

thank you! With the new extension I see the peripherals view now. For both urls:

"definitionPath":"https://pack-content.cmsis.io/NXP/K32L3A60_DFP/18.0.0/devices/K32L3A60/K32L3A60_cm4.xml", "definitionPath": "${workspaceFolder}/vscode/svd/arm_uart_pl011.svd",

Visual studio still complains wrt definitionPath property.

If I use ${workspaceFolder}/vscode/svd/arm_uart_pl011.svd then all register values are currently 0xeeeeeee

I see

<-- C (readMemory-10): {"command":"readMemory","arguments":{"memoryReference":"0x10009000","count":76},"type":"request","seq":10} --> R (readMemory-10): {"type":"response","request_seq":10,"success":true,"command":"readMemory","body":{"address":"0x10009000","unreadableBytes":76,"data":""},"seq":208}

and writing from the peripherals view into a register leads to:

<-- C (writeMemory-10): {"command":"writeMemory","arguments":{"memoryReference":"0x10009000","data":"KgAAAA=="},"type":"request","seq":10} Stopping due to fatal error: NotImplementedException: No handler implemented for request type 'WriteMemoryRequest'!

I have to check the gdbstub in the virtual system. Currently I do not see any related commands (like mem read ) arriving there. But I do not know 100% what to expect here.

kind regards Frank

On 2/18/24 18:28, Rob Moran wrote:

OK, I can see your confusion, which is my fault, sorry!

I assume you are using cortex-debug.svd-viewer https://marketplace.visualstudio.com/items?itemName=cortex-debug.svd-viewer? This is being deprecated in favour of clipse-cdt.peripheral-inspector https://marketplace.visualstudio.com/items?itemName=eclipse-cdt.peripheral-inspector (this repository).

Could you use the new extension, then try the |definitionPath| test above (pointing at the svd file url) to see if anything appears for you at all?

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thegecko commented 8 months ago

Visual studio still complains wrt definitionPath property.

Ah yes it would, because we cant control the parameters listed for the debugger you are using.

all register values are currently 0xeeeeeee

I can see the debugger is returning unreadableBytes so the debugger isnt happy with your request

No handler implemented for request type 'WriteMemoryRequest'

Your debugger doesn't support writing memory, perhaps we should handle that case in the extension?

soundart commented 8 months ago

Hi!

On 2/18/24 20:21, Rob Moran wrote:

Visual studio still complains wrt definitionPath property.
Ah yes it would, because we cant control the parameters listed for the debugger you are using.
all register values are currently 0xeeeeeee
I can see the debugger is returning |unreadableBytes| so the debugger isnt happy with your request

I debugged that and the gdbstub interprets the address as a virtual address and tries (and fails) to map it to a physical address. It returns 0xee as payload in this case.

I do not see a success flag returned so the "unreadableBytes" is surprising, but fitting in this case.

Probably I can hack around that in the gdbstub. The virtual address seem to have a lot of higher bits (bit 63-33) set. Like this in 0xffffffc00c978000

No handler implemented for request type 'WriteMemoryRequest'
Your debugger doesn't support writing memory, perhaps we should handle that case in the extension?

I am not sure what is happening there. the gdbstub implements mem write. And gdb supports it too:

https://developer.apple.com/library/archive/documentation/DeveloperTools/gdb/gdb/gdb_33.html

Maddr,length:XX... -- write mem

I do not see that packet in the wireshark dump.

I think it might be that the "higher layers" in visual studio throw that error and do not send the packet over the network at all.

I found this ReadMemoryRequest PR MIEngine#1028 https://github.com/microsoft/MIEngine/blob/main/src/OpenDebugAD7/AD7DebugSession.cs

And no "WriteMemoryRequest"

But I do not know if this is the correct place/tool/git repo/.

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thegecko commented 8 months ago

And no "WriteMemoryRequest"

Oh dear, that means the adapter wont be able to write to memory. Its a bit drastic, but you may need to switch to using a different adapter.

Ones I know of which wrap gdb:

https://github.com/eclipse-cdt-cloud/cdt-gdb-vscode (recommended as its a sister project to this one)
cortex-debug

soundart commented 8 months ago

Hi thank you very much for the help.

I am a bit surprised that memory writes are not supported. This sounds like a basic functionality.

I think all extensions (except the svd viewer) which I am using are provided by microsoft itself.

I have seen this https://github.com/eclipse-cdt-cloud/cdt-gdb-vscode/issues/119 and suspect it wont be easy to install that extension, or?

thegecko commented 7 months ago

I have seen this https://github.com/eclipse-cdt-cloud/cdt-gdb-vscode/issues/119 and suspect it wont be easy to install that extension, or?

This is a debug adapter which wraps gdb and is maintained by the eclipse foundation (along with the svd viewer here). It isn't currently published on the vscode marketplace, but I believe there are plans to do this very soon (@jonahgraham ?).

In the meantime, you can clone the repo and build it locally to get a vsix package to install.

As of yesterday, you also have another option. We have just promoted the Arm Debugger extension to version 1 here:

https://marketplace.visualstudio.com/items?itemName=Arm.arm-debugger

It doesn't use gdb, but is a full-featured debugger and could be a good alternative for you.

soundart commented 7 months ago

Thank you very much for your help!

eclipse-cdt-cloud / vscode-peripheral-inspector

how do I start the svd viewer? #18