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Eclipse OpenJ9: A Java Virtual Machine for OpenJDK that's optimized for small footprint, fast start-up, and high throughput. Builds on Eclipse OMR (https://github.com/eclipse/omr) and combines with the Extensions for OpenJDK for OpenJ9 repo.
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aladd with iconst-i2l #16929

Open knn-k opened 1 year ago

knn-k commented 1 year ago

I sometimes find JIT IL trees like shown below, typically with OSRScratchBuffer. The aladd node n49179n has an i2l node as the second child, whose child node is an iconst. It is the same for the aladd node n49183n.

Is it possible for the optimizer to simply the iconst n - i2l sequence into a lconst n node?

n49180n   istorei  <generic int shadow>[#5852  Shadow] [flags 0x603 0x0 ]                     [       0x17c55fc30] bci=[147,0,508] rc=0 vc=1426 vn=- li=107 udi=- nc=2
n49179n     aladd                                                                             [       0x17c55fbe0] bci=[147,0,508] rc=1 vc=1426 vn=- li=107 udi=- nc=2
n49176n       aload  OSRScratchBuffer[#304  MethodMeta +2536] [flags 0x10207 0x0 ]            [       0x17c55faf0] bci=[147,0,508] rc=2 vc=1426 vn=- li=107 udi=- nc=0
n49178n       i2l                                                                             [       0x17c55fb90] bci=[147,0,508] rc=1 vc=1426 vn=- li=107 udi=- nc=1
n49177n         iconst 0 (X==0 X>=0 X<=0 )                                                    [       0x17c55fb40] bci=[147,0,508] rc=1 vc=1426 vn=- li=107 udi=- nc=0 flg=0x302
n14440n     iconst 0 (X==0 X>=0 X<=0 )                                                        [       0x1680f9150] bci=[147,0,508] rc=1 vc=1426 vn=- li=107 udi=- nc=0 flg=0x302
n49184n   astorei  <generic int shadow>[#5853  Shadow] [flags 0x603 0x0 ]                     [       0x17c55fd70] bci=[147,0,508] rc=0 vc=1426 vn=- li=107 udi=- nc=2
n49183n     aladd                                                                             [       0x17c55fd20] bci=[147,0,508] rc=1 vc=1426 vn=- li=107 udi=- nc=2
n49176n       ==>aload
n49182n       i2l                                                                             [       0x17c55fcd0] bci=[147,0,508] rc=1 vc=1426 vn=- li=107 udi=- nc=1
n49181n         iconst 4 (X!=0 X>=0 )                                                         [       0x17c55fc80] bci=[147,0,508] rc=1 vc=1426 vn=- li=107 udi=- nc=0 flg=0x104
n14443n     aload  <pending push temp 0>[#2684  Auto] [flags 0x4007 0x800 ]                   [       0x1680f9240] bci=[147,0,508] rc=1 vc=1426 vn=- li=107 udi=- nc=0
knn-k commented 1 year ago

AArch64 JIT generates the following instructions for the node n49184n.

       0x131cdbfe4 000042d0 [       0x17d2f7270] 52800082 0     movzw   w2, 0x0004
       0x131cdbfe8 000042d4 [       0x17d2f73c0] f9417a80 0     ldrimmx w0, [w20, 752]      # SymRef  <pending push temp 0>[#2684  Auto +752] [flags 0x4007 0x800 ] 
       0x131cdbfec 000042d8 [       0x17d2f7450] f822c820 0     stroffx w0, [w1, w2, sxtw 0]        # SymRef  <generic int shadow>[#5853  Shadow] [flags 0x603 0x0 ]

It uses w2 as a temporary register for iconst 4. But we can throw away the movzw instruction, and change the store operation to strimmx w0, [w1, 0x4] without using the temporary register for the index in this case.

AArch64 codegen is capable of generating the store instruction with baseReg + immediate offset when the second child of aladd is lconst.