About adjusting NX_PACKET->nx_packet_prepend_ptr

[rk3399]

In the eth driver, after applying for a data packet from the packet pool, it will nx_packet_prepend_ptr += sizeof(USHORT), and then use nx_packet_prepend_ptr as the buffer first address to receive data. I want to know why +sizeof(USHORT) is needed, because this will make nx_packet_prepend_ptr not aligned to 4 bytes, and if you want to use dma to transmit data, the dma controller will automatically align this address, making the data reception error!

[bo-ms]

Hi @rk3399, Thanks for asking question. The size of Ethernet header is 14 bytes, changing the prepend_ptr two bytes is to make sure TCP/IP header 4 bytes alignment.

[rk3399]

Thanks for the reply. I hope to pass it to the first address of the 4-byte aligned to DMA, whether it is good suggestion?

[bo-ms]

Hi @rk3399 we encountered this requirement of 4-bytes alignment for some DMA, could you check if DMA supports offset? if support, you can directly set the first address as 4-bytes alignment, and set offset as 2, otherwise, you may need to prepare the buffer to DMA to receive data, then copy it into packet.

[rk3399]

In fact, I encountered this problem when using USBx to drive the CDC-ECM network card. On the STM32H7 series MCU, the USB DMA controller requires the transmission start address to be 32bit aligned. Does USBx have a solution for this problem?

[xiaocq2001]

Currently USBX Host Controller Driver (HCD) calls ST's BSP HALHCD API to issue data transfer. Maybe you can try to disable DMA in HALHCD on initialization. This way FIFO is used and unaligned address should be OK.

[rk3399]

Currently USBX Host Controller Driver (HCD) calls ST's BSP HALHCD API to issue data transfer. Maybe you can try to disable DMA in HALHCD on initialization. This way FIFO is used and unaligned address should be OK.

Disabling DMA does work. But this will cause CDC-ECM to occupy almost all cpu resources (each NCK will generate an interrupt), and other tasks will not be executed

[xiaocq2001]

Suggestion:

1. Check with ST to learn if their USB DMA controller has unaligned address offset support.
2. If bulk transfer buffer address is not aligned, create aligned cache safe buffer and copy data, this also creates overhead.

[rk3399]

Suggestion:

1. Check with ST to learn if their USB DMA controller has unaligned address offset support.
2. If bulk transfer buffer address is not aligned, create aligned cache safe buffer and copy data, this also creates overhead.

Thank you for your suggestion!