Open Spencer-Comin opened 3 days ago
A 32 bit load instruction followed by a zero/sign extend instruction can be replaced with an equivalent load and zero/sign extend instruction.
LGFR R1,R1
LLGFR R1,R1
L R1,M1
LGF R1,M1
LLGF R1,M1
LH R1,M1
LGH R1,M1
LLH R1,M1
LLGH R1,M1
LB R1,M1
LGB R1,M1
LLC R1,M1
LLGC R1,M1
XR R1,R1
XGR R1,R1
IILF R1,I1
LGFI R1,I1
LLILF R1,I1
LHI R1,I1
LGHI R1,I1
LLILF R1,I2
LR R1,R2
LGFR R1,R2
LLGFR R1,R2
LGR R1,R2
*M1 is an arbitrary memory reference **I2 is I1 sign extended from 16 to 32 bits
M1
I2
I1
A 32 bit load instruction followed by a zero/sign extend instruction can be replaced with an equivalent load and zero/sign extend instruction.
LGFR R1,R1
LLGFR R1,R1
L R1,M1
*LGF R1,M1
*LLGF R1,M1
*LH R1,M1
*LGH R1,M1
*LLH R1,M1
*LLGH R1,M1
*LB R1,M1
*LGB R1,M1
*LLC R1,M1
*LLGC R1,M1
*XR R1,R1
XGR R1,R1
XGR R1,R1
IILF R1,I1
LGFI R1,I1
LLILF R1,I1
LHI R1,I1
LGHI R1,I1
LLILF R1,I2
**LR R1,R2
LGFR R1,R2
LLGFR R1,R2
LGR R1,R2
LGFR R1,R2
LLGFR R1,R2
*
M1
is an arbitrary memory reference **I2
isI1
sign extended from 16 to 32 bits