Refactor simulator to verify instead of evaluate

[ed255]

Currently the simulator is implemented by updating the state of the RISC-V machine. It would be a better match with the final circuit if instead it verifies the state change. So each simulator instruction would receive the arguments (instruction arguments, state, state_next) And verify that state_next is correct considering state, instruction and the instruction arguments.

For example, instead of doing:

self.pc = self.pc + 4;

it would be:

assert_eq(state_next.pc, state.pc + 4);