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edaa-org / pyEDAA.ProjectModel

An abstract model of EDA tool projects.
https://edaa-org.github.io/pyEDAA.ProjectModel
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Moving more Version classes to a separate repository? #2

Closed Paebbels closed 3 years ago

Paebbels commented 3 years ago

I moved VHDLVersion to pyVHDLModel. See https://github.com/VHDL/pyVHDLModel/pull/29.

I would like to kickout VerilogVersion and SystemVerilogVersion as well to a pySystemVerilogModel repository. What do you think?

Where to host it? Just for now at github.com/Paebbels or directly at github.com/HDL?

umarcor commented 3 years ago

I think that a pySystemVerilogModel module/repo makes sense. However, I'm unsure about creating it in org 'hdl'. I would propose to create it here for now: edaa-org/pySystemVerilogModel.

The bigger picture is that several projects for parsing SV exist (such as Verible or Surelog). Precisely, Surelog is tightly coupled to the Universal Hardware Data Model (UHDM). All three repos (verible, surelog and uhdm) were recently moved to org github.com/chipsalliance. Therefore, it would make sense to have chipsalliance/pySystemVerilogModel, if maintainers/developers of Verible/Surelog/UHDM are to provide a Python interface (similarly to how pyGHDL, pyVHDLParser are backend candidates for pyVHDLModel).

umarcor commented 3 years ago

FTR, pySystemVerilogModel was created and the Version classes were moved already. However, we are considering to rename the repo and the Python module from pySystemVerilogModel to pySVModel.

Paebbels commented 3 years ago

The package has been renamed to pySVModel.