Verilog include file is missing

[RasmusGOlsen]

There should be a way to specify if the VerilogSourceFile or SystemVerilogSource file is an included file. I suggest this can be a property in the class or a new class.

[Paebbels]

I'm not into Verilog so much. I know there are sources (*.v/*.sv) and headers (*.vh/*.svh).

Are include files further files?

I would model it so:

• If it's a separate file extension, it's a new class.
• If it's a file and how it's used, I would either use a fixed Python property if defined in the standard or a user-defined key-value pair.

E.g. the latter could be used in a VHDL context if a utils.pkg.vhdl is added. It's an ordinary VHDL source file, but it contains a package, thus the file name. It could be marked with a key-value pair and multiple package files could be identified by a filtered search checking key-value pairs.

[RasmusGOlsen]

Typically you would give the Verilog include files the .vh / .svh file extension to easily distinguish them from regular Verilog files. A Verilog include file is not compiled by itself. The Verilog preprocessor will do text substitution, i.e. copy/paste the included file content into the Verilog files that include them. Some tools don't specify the included file at all, but instead, specify directories for the Verilog precompiler to search for included files. I think Verilog is inspired by the C language which also operates with a precompiler and include files.

[RasmusGOlsen]

I think I would prefer it's a boolean attribute to the VerilogSourceFile and SystemVerilogSourceFile classes since the file extension is not the determining factor.

[Paebbels]

Latest changes are on dev branch.