edaa-org / pyEDAA.ProjectModel

An abstract model of EDA tool projects.
https://edaa-org.github.io/pyEDAA.ProjectModel
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Verilog needs library, and include file information #63

Open RasmusGOlsen opened 11 months ago

RasmusGOlsen commented 11 months ago

The VerilogSourceFile and SystemVerilogSourceFile need a library attribute, the same as in the VHDLSourceFile. Could you add this to the HDLSourceFile class and remove it from the VHDLSourceFile class? This way, the VerilogSourceFile and SystemVerilogSourceFile will also inherit the library attribute. When you have the Verilog version it is also not necessary to have both a VerilogSourceFile and SystemVerilogSourceFile class. There needs to be either a Verilog include attribute or a VerilogIncludeFile class to handle Verilog include files.

class HDLIncludeFile(SourceFile):
    pass

class VerilogIncludeFile(HDLIncludeFile, HumanReadableContent):
    pass

class HDLSourceFile(SourceFile):
    _library: HDLLibrary

class VHDLSourceFile(HDLSourceFile, HumanReadableContent):
    _version: VHDLVersion

class VerilogSourceFile(HDLSourceFile, HumanReadableContent):
    _version: VerilogVersion
RasmusGOlsen commented 11 months ago

I wondering about the _version attribute. If you have the _version attribute maybe you don't need VHDL or Verilog classes but just the HDL class.

class HDLIncludeFile(SourceFile):
    pass

class HDLSourceFile(SourceFile):
    _version: HDLVersion
    _library: HDLLibrary

If you just wish multiple classes then may drop the _version and implement multiple classes for VHDL and Verilog.

class HDLIncludeFile(SourceFile):
    pass

class HDLSourceFile(SourceFile):
    _library: HDLLibrary

class VerilogIncludeFile(HDLIncludeFile, HumanReadable):
    pass

class Verilog(HDLSourceFile, HumanReadable):
    pass

class VerilogSourceFile95(Verilog):
   pass

class VerilogSourceFile2001(Verilog):
    pass

class SystemVerilogSourceFile(Verilog):
    pass

class SystemVerilogSourceFile2005(SystemVerilog):
    pass

class SystemVerilogSourceFile2009(SystemVerilog):
    pass

class VHDLSourceFile(HDLSourceFile, HumanReadable):
    pass

class VHDLSourceFile87(VHDLSourceFile):
    pass

class VHDLSourceFile93(VHDLSourceFile):
    pass

class VHDLSourceFile2008(VHDLSourceFile):
    pass