MyHDL support

[cfelton]

MyHDL is a Python based hardware description language that supports cosimulation with Verilog simulators. MyHDL is a mature and popular Python based HDL and verification environment. The MyHDL development repo is on bitbucket.

The documents outline MyHDL and the cosimulation specifics can be found here.

MyHDL contains an embedded simulator, HDL can be written and simulated completely in the Python environment.

The MyHDL based design flow (Python+MyHDL verification and MyHDL HDL):

• write the python+myhdl verification
• write the myhdl design
• run the myhdl simulator
• convert and cosimulation, [example](http://www.myhdl.org/doku.php/cookbook:sinecomp).

The Verilog verification flow (Python+MyHDL verification and Verilog HDL):

• write the python verification
• write a wrapper module for the Verilog
• convert the wrapper to Verilog generating the dut wrapper
• run the simulator with the myhdl.vpi and the dut wrapper

MyHDL requires Python 2.x, 2.6 or greater.

[getvictor]

For co-simulation, I see that the user must hardcode the simulation command to execute. This somewhat conflicts with the current EDA Playground approach. Currently, simulator commands and switches are provided by the platform, and the user can switch simulators with a click.

Is there a MyHDL supported way to abstract the simulation command from the user? So that the same Python code can potentially run on any simulator.

[cfelton]

Ok, what we probably need is a python script that can take the platform switches and execute the cosimulation. Would that be reasonable? It would not be too much work to put together a python script that takes as switches (command line arguments) that define the simulator, the module, etc.

Example:

import os
import argparse
from myhdl import Cosimulation,Simulation

parser = argparse.ArgumentParser()
parser.add_argument('--sim', choices=('iver','mti'))
parser.add_argument('--tb')
parser.add_argument('--dut')
# duplicate 
args = parser.parse_args()
print(args)

# get the dut 
exec("from %s import *"%(args.tb))
exec("from %s import *"%(args.dut))
exec("tbco,portmap = %s()"%(args.tb))
exec("toVerilog(%s,**portmap)"%(args.dut))

# build the commands needed
cmd = "iverilog -o %s %s.v tb_%s"%(args.dut,args.dut,args.dut)
os.system(cmd)
tbdut = Cosimulation("vvp -m ./myhdl.vpi %s"%(args.dut), **portmap)
Simulation((tbco,tbdut)).run()

I put this together insanely quick (i.e. didn't check much). Here are the test and dut that would go with it.

from myhdl import *
def bin2gray(b, g):
    """ Gray encoder.
    b -- input intbv signal, binary encoded
    g -- output intbv signal, gray encoded
    """
    width = len(b)-1
    @always_comb
    def logic():
        for i in range(width):
            g.next[i] = b[i+1] ^ b[i]
    return logic

from myhdl import *
def test_bin2gray():
    b = Signal(intbv(0)[4:])
    g = Signal(intbv(0)[4:])

    @instance
    def tb_stim():
        for ii in xrange(2**len(b)):
            b.next = b + 1
            print(g)
            yield delay(10)

    # the test returns the generators (coroutines and a portmap
    return (tb_stim,), dict(b=b,g=g)

It could be run from the command line like:

python simcli.py --sim=iver --tb=test_bin2gray --dut=bin2gray

This should work to grab all the parameters from and interface and then kick off a simulation. Might be a little pain having to reproduce some of the simulator switches in the script.

[getvictor]

Yes, that would work, if that's the easiest thing to do.

Can this type of script be included in the official MyHDL repository? Seems like co-simulation needs to support 2 usecases:

• Python Testbench and Python Design (which is converted to Verilog by the script)
• Python Testbench and Verilog Design

I'd like to minimize/eliminate the custom code that EDA Playground needs to run a tool.

As an enhancement, it would be nice if tb and dut didn't have to be explicitly specified. I like that for cocotb you don't need to specify any module names on EDA Playground.

Meanwhile, for EDA Playground, I'll work on adding the base usecase of Python Design and Python Testbench simulated completely in Python MyHDL.

[getvictor]

MyHDL (w/o co-simulation) is now available on EDA Playground. Here a couple example links: http://www.edaplayground.com/s/example/226 http://www.edaplayground.com/s/example/227

I welcome additional examples to put on the front page. Also, links to EDA Playground can be used in MyHDL documentation/examples/tutorials.

Please take a look.

[cfelton]

Wow - that was fast! I tested it out: http://www.edaplayground.com/s/130/229

I believe we should be able to add cosimulation scripts to the myhdl package. When I have a little more time, I will explore a couple options, and propose it to the myhdl community.

[getvictor]

Yes, software development is way faster than hardware development :)

Would you like me to put your strobe example on the front page? If so, any additional documentation for it?

[cfelton]

I created a RAM version similar to the others, this is a good example to include in the "example list"; http://www.edaplayground.com/s/130/230

Time permitting I will create some documentation and more examples, but it might be a little bit before I have sufficient time.

[getvictor]

I added the example to the front page.

Let me know if you'd like to add more examples or features for MyHDL, and when the co-simulation scripts are ready. You can reach me at victor at victoreda.com

Meanwhile, I'll close this particular issue.