Timing mismatch between TX and RX start bit

[M0stafaRady]

The 2 modules UART_TX and UART_RX have 2 different timing implementation for the start bit. The fsm in UART_RX waits half the number of samples, however the same state in the UART_TX waits the full number of samples. https://github.com/efabless/EF_UART/blob/a99c27adaf30e3da114f6e19d30105970e83a741/hdl/rtl/EF_UART.v#L320-L322

https://github.com/efabless/EF_UART/blob/a99c27adaf30e3da114f6e19d30105970e83a741/hdl/rtl/EF_UART.v#L487-L490

[M0stafaRady]

After reviewing the implementation. this seems to be intended so the receiving side would sample at the half bit received. @shalan is this the case ?

[shalan]

This is how it works. We sample at the middle of the received bit. That is why we wait for the time of a half bit when we receive the start bit.