Glitch fliter doesn't work as intended

[M0stafaRady]

The glitch filter logic don't ignore the effect of the glitches in all the possible cases. From the wave form below a glitch of 1 is inserted in a bit of 0 and that makes the out value to be 1 instead of 0. Because the all_zeros and all_ones conditions aren't valid the value doesn't change and this kept the old/wrong value. arrow point to the glitch

filter code used: https://github.com/shalan/IP_Utilities/blob/259117368d3fb0638032219220550962a80af2f6/rtl/aucohl_lib.v#L105-L141

suggested fix: update the filter to get rid of the glitch by ignoring small pulse widths. Like the code below generated by AI

`module uart_glitch_filter ( input wire clk, // Clock input input wire reset, // Reset input input wire rx_in, // UART RX input output reg rx_out // Filtered UART RX output );

// Parameters
parameter GLITCH_WIDTH = 10; // Define glitch width threshold

// Internal signals
reg [3:0] counter = 0; // 4-bit counter, adjust size if needed
reg rx_reg = 0;

always @(posedge clk or posedge reset) begin
    if (reset) begin
        // Reset state
        rx_reg <= 0;
        counter <= 0;
        rx_out <= 0;
    end else begin
        if (rx_in != rx_reg) begin
            // Reset counter on RX edge
            counter <= 0;
        end else begin
            if (counter < GLITCH_WIDTH) begin
                // Increment counter
                counter <= counter + 1;
            end
        end
        if (counter >= GLITCH_WIDTH) begin
            // Update output if above glitch threshold
            rx_out <= rx_in;
        end
    end
end

endmodule `

[shalan]

The glitch filter is supposed to produce "1" or "0" when it sees a number of consecutive 1s or 0s based on the sampling rate. Your scenario does not honor the sampling rate. @M0stafaRady

[shalan]

The glitch filter assumes that the glitches are happening as the signal changes its level.