unmapped cells in synthesis

[M0stafaRady]

got error from yosys when generating the gl of UART with wrapper files in synthesis:

• /hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
• /hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
• /hdl/rtl/bus_wrappers/EF_UART_WB.pp.v
• /rtl/aucohl_lib.v
• /rtl/aucohl_rtl.vh
• //hdl/rtl/EF_UART.v

Errors from the log:

57. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_2 (noninv, pins=3, area=21.27) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

[shalan]

@M0stafaRady Are you sure that the netlist contains $ cells ?

I synthesized the RTL and the netlist is good to me. Here is the output from yosys stat command:

Number of cells: 2115 sky130_fd_sc_hda2111oi_0 3 sky130_fd_sc_hda211o_1 1 sky130_fd_sc_hda211oi_1 5 sky130_fd_sc_hda21boi_0 7 sky130_fd_sc_hda21o_1 1 sky130_fd_sc_hda21oi_1 84 sky130_fd_sc_hda221o_1 3 sky130_fd_sc_hda221oi_1 2 sky130_fd_sc_hda222oi_1 2 sky130_fd_sc_hda22o_1 8 sky130_fd_sc_hda22oi_1 5 sky130_fd_sc_hda2bb2oi_1 1 sky130_fd_sc_hda31o_1 1 sky130_fd_sc_hda31oi_1 8 sky130_fd_sc_hda32o_1 5 sky130_fd_sc_hda32oi_1 1 sky130_fd_sc_hda41oi_1 3 sky130_fd_sc_hdand2_0 21 sky130_fd_sc_hdand3_1 11 sky130_fd_sc_hdand3b_1 1 sky130_fd_sc_hdand4_1 2 sky130_fd_sc_hdclkinv_1 124 sky130_fd_sc_hddfrtp_1 194 sky130_fd_sc_hddfstp_2 24 sky130_fd_sc_hddfxtp_1 291 sky130_fd_sc_hdlpflow_inputiso1p_1 17 sky130_fd_sc_hd__lpflow_isobufsrc_1 25 sky130_fd_sc_hdmaj3_1 5 sky130_fd_sc_hdmux2_1 367 sky130_fd_sc_hdmux2i_1 23 sky130_fd_sc_hdmux4_2 20 sky130_fd_sc_hdnand2_1 134 sky130_fd_sc_hdnand2b_1 8 sky130_fd_sc_hdnand3_1 37 sky130_fd_sc_hdnand3b_1 1 sky130_fd_sc_hdnand4_1 22 sky130_fd_sc_hdnand4b_1 1 sky130_fd_sc_hdnor2_1 151 sky130_fd_sc_hdnor2b_1 1 sky130_fd_sc_hdnor3_1 39 sky130_fd_sc_hdnor3b_1 5 sky130_fd_sc_hdnor4_1 25 sky130_fd_sc_hdnor4b_1 7 sky130_fd_sc_hdnor4bb_1 1 sky130_fd_sc_hdo2111a_1 1 sky130_fd_sc_hdo2111ai_1 4 sky130_fd_sc_hdo211a_1 1 sky130_fd_sc_hdo211ai_1 6 sky130_fd_sc_hdo21a_1 2 sky130_fd_sc_hdo21ai_0 109 sky130_fd_sc_hdo21bai_1 28 sky130_fd_sc_hdo221a_1 1 sky130_fd_sc_hdo221ai_1 2 sky130_fd_sc_hdo22a_1 4 sky130_fd_sc_hdo22ai_1 136 sky130_fd_sc_hdo2bb2ai_1 2 sky130_fd_sc_hdo31a_1 1 sky130_fd_sc_hdo31ai_1 12 sky130_fd_sc_hdo41ai_1 6 sky130_fd_sc_hdor3_1 9 sky130_fd_sc_hdor3b_1 4 sky130_fd_sc_hdor4_1 5 sky130_fd_sc_hdor4b_1 1 sky130_fd_sc_hdxnor2_1 44 sky130_fd_sc_hdxnor3_1 1 sky130_fd_sc_hd__xor2_1 39

It is clear that there is nothing unmapped!