Closed M0stafaRady closed 5 months ago
When the data bits length is configured with 9 the transmitting and receiving FSM would stuck forever at the data_st state because the length of regs count_next and count_reg are only 3 bits so the condition to exit the stateif(count_next == (data_size - 1))will never be triggered. https://github.com/efabless/EF_UART/blob/a99c27adaf30e3da114f6e19d30105970e83a741/hdl/rtl/EF_UART.v#L499-L515
data_st
count_next
count_reg
if(count_next == (data_size - 1))
When the data bits length is configured with 9 the transmitting and receiving FSM would stuck forever at the
data_ststate because the length of regscount_nextandcount_regare only 3 bits so the condition to exit the stateif(count_next == (data_size - 1))will never be triggered. https://github.com/efabless/EF_UART/blob/a99c27adaf30e3da114f6e19d30105970e83a741/hdl/rtl/EF_UART.v#L499-L515