The test chip GPIO layout has gpio_control_in_1[4] and gpio_control_in_1[5] swapped.
gpio_control_in_1[4] should connect to mprj_io[12] and gpio_control_in_1[5] should connect to mrpj_io[13].
It is not clear how these got swapped. Is the error in the source verilog?
RTimothyEdwards
commented
1 year ago
The test chip GPIO layout has gpio_control_in_1[4] and gpio_control_in_1[5] swapped. gpio_control_in_1[4] should connect to mprj_io[12] and gpio_control_in_1[5] should connect to mrpj_io[13]. It is not clear how these got swapped. Is the error in the source verilog?