Fix GL/RTL and DEF mismatches in `chip_io` and `gpio_defaults_block`

[RTimothyEdwards]

Note that the error in the gpio_defaults_block cells only passes verification because we don't have specific verification for some of the bits which alter settings of the I/O that are not obviously detectable in verilog simulation, like output drive strength. The bits 7, 8, and 9. That makes sense for bits 8 and 9, which are the drive strength. However, it should have been possible to detect the error in bit 7, which would require a testbench that checks the testable state of the I/Os on power-up with specific defaults configurations (in this case, a pull-up setting).

[RTimothyEdwards]

i.e., it would have been possible to catch this error in simulation with a testbench in RTL verilog that passes in an alternative user_defines.v file and then checks if the GPIO are in the intended state (checking user/management, pullup/pulldown, input/output).

[passant5]

reverted https://github.com/efabless/caravel-gf180mcu/commit/af9eb3f69e1de57c16e277d9fc9e7eb75da480cb