Signals that should not be inputs to buffers are buffered

[RTimothyEdwards]

\mgmt_buffers.mprj_ack_i_user
\mgmt_buffers.mprj_dat_i_user[0:10]
\mgmt_buffers.mprj_dat_i_user[19]
\mgmt_buffers.user_irq_core[0:2]
\user_io_oeb[1:6]
\user_io_out[1:2]

e.g., in verilog/gl/caravel_core.v:

 gf180mcu_fd_sc_mcu7t5v0__buf_4 wire1727 (.I(\mgmt_buffers.mprj_ack_i_user ),
    .Z(net1727),
    .VDD(VDD),
    .VNW(VDD),
    .VPW(VSS),
    .VSS(VSS));

This buffer, and all of the others connected to the signals above that have previously (in the sky130 version of caravel) been identified as needing to remain unbuffered, should be marked in some configuration file to prevent the flow from adding buffers on them. I believe that for the last sky130 version of caravel, the NAND gates were forced to be close to the pin so that no wire-length-mitigating buffer would need to be inserted; such buffers can be added on the other side of the gate. As is evident from the list at top, only some of the signals are being buffered, indicating that they are buffered due to a long wire distance from the pin to the gate.

[jeffdi]

this needs to be fixed still