Modified the MiM cap layout to add the capacitor length marker that is apparently required by the Calibre LVS deck to get an LVS match on the POR layout.
This mask layer does not correspond to a physical manufacturing mask, and does not affect the current tape-out. It only affects the ability to run LVS with Calibre on the full chip without black-boxing the POR.
Modified the MiM cap layout to add the capacitor length marker that is apparently required by the Calibre LVS deck to get an LVS match on the POR layout.
This mask layer does not correspond to a physical manufacturing mask, and does not affect the current tape-out. It only affects the ability to run LVS with Calibre on the full chip without black-boxing the POR.