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efabless / caravel-gf180mcu

This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
Apache License 2.0
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gfmpw-1: filltie count mismatch in gpio_defaults_block #191

Open d-m-bailey opened 8 months ago

d-m-bailey commented 8 months ago

Not a manufacturing problem, but the filltie cell counts differ between the gpio_defaults_block layout(5) and verilog(6).

netgen (mistakenly) flattens these black-boxed cells, so there is currently no error in LVS.

Probably fixable by modifying caravel/verilog/gl/gpio_defaults_block.v

   /* 6 fillties */
   gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_0 (.VDD(VDD), .VSS(VSS));
   gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_1 (.VDD(VDD), .VSS(VSS));
   gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_2 (.VDD(VDD), .VSS(VSS));
   gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_3 (.VDD(VDD), .VSS(VSS));
   gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_4 (.VDD(VDD), .VSS(VSS));
   gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_5 (.VDD(VDD), .VSS(VSS));

Layout counts

  gpio_defaults_block_007 2
   gf180mcu_fd_sc_mcu7t5v0__tieh 10
   gf180mcu_fd_sc_mcu7t5v0__tiel 10
   gf180mcu_fd_sc_mcu7t5v0__endcap 7
   gf180mcu_fd_sc_mcu7t5v0__fillcap_4 8
   gf180mcu_fd_sc_mcu7t5v0__filltie 5