chip_io.v gl is missing some ports

[mo-hosni]

chip_io.v gl is missing ports such as const_zeroand const_one.

[RTimothyEdwards]

I didn't create the gate level verilog for chip_io. It was created from the DEF file, maybe by Kareem or Marwan? They have a script somewhere, or maybe they did it manually, to process the DEF file through yosys and generate a gate-level verilog netlist. But yosys doesn't read DEF so I'm not sure what tools they're using (other than that the gate level netlist has a header from yosys in it, so it definitely got passed through yosys as the final step).