Closed mo-hosni closed 1 year ago
caravel_core is now clean if we abstract SRAM cells, user_project_wrapper and simple_por. Issue for SRAM: https://github.com/efabless/caravel-gf180mcu/issues/87 Issue for simple_por: https://github.com/efabless/caravel-gf180mcu/issues/79
caravel_core
is LVS clean when black boxing simple_por
and user_project_wrapper
=
There are net mismatches in the nets on the SRAM interface in the abstract LVS. I reviewed some of them and the layout was correct. This might be a problem with the extraction from LEF, not the layout.
A device-level LVS is needed.