Created gate-level netlists of user_id_programming and gpio_defaults_block

[RTimothyEdwards]

Created gate-level netlists of the user_id_programming and gpio_defaults_block cells to be compatible with the scripts that do the modifications during the chip assembly process.

[RTimothyEdwards]

@M0stafaRady : You will need an updated PDK from the most recent version of open_pdks, which adds the VPW and VNW pins to all the standard cells that require them.

[RTimothyEdwards]

Based on feedback from Passant, I will update the other views (DEF, mainly, but also .mag and GDS) so that the names of the cell instances match the names of the cell instances of these cells in the verilog/gl/ files.

[RTimothyEdwards]

@marwaneltoukhy @M0stafaRady : The new commit ensures that all views of user_id_programming and gpio_defaults_block* agree on the names of instances and the names of nets.