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efabless / caravel-gf180mcu

This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
Apache License 2.0
8 stars 8 forks source link

Extraction issue in SRAM #77

Closed marwaneltoukhy closed 1 year ago

marwaneltoukhy commented 1 year ago

Extracting SRAM using magic doesn't show VDD as a pin in spice, it only shows VSS. When doing LVS on caravel_core shows that the VDD and VSS are shorted, when removing SRAM wrapper it doesn't have a short anymore.

extracted spice:

.subckt gf180mcu_fd_ip_sram__sram512x8m8wm1 CLK D[0] A[8] A[7] A[2] A[1] A[0] Q[2]
+ Q[3] CEN A[5] A[6] A[4] WEN[3] D[7] Q[7] D[3] D[1] D[2] A[3] Q[1] Q[6] D[5] Q[4]
+ WEN[5] WEN[2] WEN[1] WEN[4] WEN[7] WEN[6] D[4] D[6] Q[5] Q[0] GWEN WEN[0] VSS
Xlcol4_512_512x8m81_0 lcol4_512_512x8m81_0/WL[32] lcol4_512_512x8m81_0/WL[33] lcol4_512_512x8m81_0/WL[34]
+ lcol4_512_512x8m81_0/WL[38] lcol4_512_512x8m81_0/WL[39] lcol4_512_512x8m81_0/WL[35]
+ lcol4_512_512x8m81_0/WL[36] lcol4_512_512x8m81_0/WL[37] lcol4_512_512x8m81_0/WL[40]
+ lcol4_512_512x8m81_0/WL[41] lcol4_512_512x8m81_0/WL[42] lcol4_512_512x8m81_0/WL[43]
+ lcol4_512_512x8m81_0/WL[44] lcol4_512_512x8m81_0/WL[45] lcol4_512_512x8m81_0/WL[46]
+ lcol4_512_512x8m81_0/WL[47] lcol4_512_512x8m81_0/WL[48] lcol4_512_512x8m81_0/WL[49]
+ lcol4_512_512x8m81_0/WL[50] lcol4_512_512x8m81_0/WL[51] lcol4_512_512x8m81_0/WL[52]
+ lcol4_512_512x8m81_0/WL[53] lcol4_512_512x8m81_0/WL[54] lcol4_512_512x8m81_0/WL[55]
+ lcol4_512_512x8m81_0/WL[56] lcol4_512_512x8m81_0/WL[57] lcol4_512_512x8m81_0/WL[58]
+ lcol4_512_512x8m81_0/WL[59] lcol4_512_512x8m81_0/WL[60] lcol4_512_512x8m81_0/WL[61]
+ lcol4_512_512x8m81_0/WL[62] lcol4_512_512x8m81_0/WL[63] lcol4_512_512x8m81_0/WL[25]
+ lcol4_512_512x8m81_0/WL[24] lcol4_512_512x8m81_0/WL[23] lcol4_512_512x8m81_0/WL[22]
+ lcol4_512_512x8m81_0/WL[21] lcol4_512_512x8m81_0/WL[20] lcol4_512_512x8m81_0/WL[19]
+ lcol4_512_512x8m81_0/WL[18] lcol4_512_512x8m81_0/WL[17] lcol4_512_512x8m81_0/WL[16]
+ lcol4_512_512x8m81_0/WL[15] lcol4_512_512x8m81_0/WL[14] lcol4_512_512x8m81_0/WL[13]
+ lcol4_512_512x8m81_0/WL[12] lcol4_512_512x8m81_0/WL[11] lcol4_512_512x8m81_0/WL[10]
+ lcol4_512_512x8m81_0/WL[9] lcol4_512_512x8m81_0/WL[8] lcol4_512_512x8m81_0/WL[7]
+ lcol4_512_512x8m81_0/WL[6] lcol4_512_512x8m81_0/WL[5] lcol4_512_512x8m81_0/WL[4]
+ lcol4_512_512x8m81_0/WL[3] lcol4_512_512x8m81_0/WL[2] lcol4_512_512x8m81_0/WL[1]
+ lcol4_512_512x8m81_0/WL[0] lcol4_512_512x8m81_0/WL[31] lcol4_512_512x8m81_0/WL[30]
+ lcol4_512_512x8m81_0/WL[29] lcol4_512_512x8m81_0/WL[28] lcol4_512_512x8m81_0/WL[27]
+ lcol4_512_512x8m81_0/WL[26] lcol4_512_512x8m81_0/men lcol4_512_512x8m81_0/ypass[0]
+ lcol4_512_512x8m81_0/ypass[1] lcol4_512_512x8m81_0/ypass[2] lcol4_512_512x8m81_0/ypass[3]
+ lcol4_512_512x8m81_0/ypass[4] lcol4_512_512x8m81_0/ypass[5] lcol4_512_512x8m81_0/ypass[6]
+ lcol4_512_512x8m81_0/ypass[7] VSS lcol4_512_512x8m81_0/GWEN lcol4_512_512x8m81_0/GWE
+ lcol4_512_512x8m81_0/pcb[2] lcol4_512_512x8m81_0/pcb[3] lcol4_512_512x8m81_0/pcb[0]
+ lcol4_512_512x8m81_0/pcb[1] VSS WEN[0] lcol4_512_512x8m81_0/WEN[2] WEN[2] WEN[3]
+ D[0] D[1] D[3] D[2] Q[0] Q[1] Q[2] Q[3] xdec64_512x8m81_0/LWL[62] xdec64_512x8m81_0/LWL[29]
+ xdec64_512x8m81_0/LWL[46] xdec64_512x8m81_0/LWL[63] VSS xdec64_512x8m81_0/LWL[47]
+ xdec64_512x8m81_0/LWL[48] rcol4_512_512x8m81_0/GWEN xdec64_512x8m81_0/LWL[49] D[1]
+ xdec64_512x8m81_0/LWL[10] xdec64_512x8m81_0/LWL[11] xdec64_512x8m81_0/LWL[12] xdec64_512x8m81_0/LWL[13]
+ xdec64_512x8m81_0/LWL[30] xdec64_512x8m81_0/LWL[14] xdec64_512x8m81_0/LWL[31] VSS
+ xdec64_512x8m81_0/LWL[15] xdec64_512x8m81_0/LWL[32] xdec64_512x8m81_0/LWL[0] xdec64_512x8m81_0/LWL[16]
+ xdec64_512x8m81_0/LWL[33] WEN[1] xdec64_512x8m81_0/LWL[50] xdec64_512x8m81_0/LWL[1]
+ VSS xdec64_512x8m81_0/LWL[17] xdec64_512x8m81_0/LWL[34] xdec64_512x8m81_0/LWL[2]
+ xdec64_512x8m81_0/LWL[51] xdec64_512x8m81_0/LWL[18] xdec64_512x8m81_0/LWL[35] VSS
+ xdec64_512x8m81_0/LWL[3] xdec64_512x8m81_0/LWL[52] xdec64_512x8m81_0/LWL[19] xdec64_512x8m81_0/LWL[36]
+ xdec64_512x8m81_0/LWL[53] xdec64_512x8m81_0/LWL[4] xdec64_512x8m81_0/LWL[37] xdec64_512x8m81_0/LWL[54]
+ xdec64_512x8m81_0/LWL[5] xdec64_512x8m81_0/LWL[38] xdec64_512x8m81_0/LWL[6] xdec64_512x8m81_0/LWL[55]
+ xdec64_512x8m81_0/LWL[39] xdec64_512x8m81_0/LWL[7] xdec64_512x8m81_0/LWL[56] VSS
+ xdec64_512x8m81_0/LWL[8] xdec64_512x8m81_0/LWL[57] xdec64_512x8m81_0/LWL[58] xdec64_512x8m81_0/LWL[9]
+ xdec64_512x8m81_0/LWL[59] xdec64_512x8m81_0/men lcol4_512_512x8m81_0/col_512a_512x8m81_0/saout_m2_512x8m81_1/mux821_512x8m81_0/ypass_gate_512x8m81_6/pcb
+ xdec64_512x8m81_0/LWL[20] xdec64_512x8m81_0/LWL[21] control_512x8_512x8m81_0/LYS[0]
+ lcol4_512_512x8m81_0/col_512a_512x8m81_0/saout_R_m2_512x8m81_1/sa_512x8m81_0/pcb
+ rcol4_512_512x8m81_0/GWE VSS xdec64_512x8m81_0/LWL[22] control_512x8_512x8m81_0/LYS[1]
+ xdec64_512x8m81_0/LWL[23] xdec64_512x8m81_0/LWL[40] control_512x8_512x8m81_0/LYS[2]
+ xdec64_512x8m81_0/LWL[24] xdec64_512x8m81_0/LWL[41] control_512x8_512x8m81_0/LYS[3]
+ xdec64_512x8m81_0/LWL[25] lcol4_512_512x8m81_0/col_512a_512x8m81_0/saout_m2_512x8m81_0/mux821_512x8m81_0/ypass_gate_512x8m81_6/pcb
+ xdec64_512x8m81_0/LWL[42] control_512x8_512x8m81_0/LYS[4] xdec64_512x8m81_0/LWL[26]
+ control_512x8_512x8m81_0/LYS[5] xdec64_512x8m81_0/LWL[43] VSS xdec64_512x8m81_0/LWL[60]
+ VSS lcol4_512_512x8m81_0/col_512a_512x8m81_0/saout_R_m2_512x8m81_0/sa_512x8m81_0/pcb
+ xdec64_512x8m81_0/LWL[27] control_512x8_512x8m81_0/LYS[6] xdec64_512x8m81_0/LWL[44]
+ xdec64_512x8m81_0/LWL[61] VSS xdec64_512x8m81_0/LWL[28] control_512x8_512x8m81_0/LYS[7]
+ xdec64_512x8m81_0/LWL[45] VSS VSS lcol4_512_512x8m81
Xrcol4_512_512x8m81_0 rcol4_512_512x8m81_0/WL[32] rcol4_512_512x8m81_0/WL[33] rcol4_512_512x8m81_0/WL[34]
+ rcol4_512_512x8m81_0/WL[35] rcol4_512_512x8m81_0/WL[36] rcol4_512_512x8m81_0/WL[37]
+ rcol4_512_512x8m81_0/WL[42] rcol4_512_512x8m81_0/WL[44] rcol4_512_512x8m81_0/WL[46]
+ rcol4_512_512x8m81_0/WL[48] rcol4_512_512x8m81_0/WL[50] rcol4_512_512x8m81_0/WL[52]
+ rcol4_512_512x8m81_0/WL[54] rcol4_512_512x8m81_0/WL[56] rcol4_512_512x8m81_0/WL[57]
+ rcol4_512_512x8m81_0/WL[59] xdec64_512x8m81_0/DRWL rcol4_512_512x8m81_0/WL[61] rcol4_512_512x8m81_0/WL[51]
+ rcol4_512_512x8m81_0/WL[29] rcol4_512_512x8m81_0/WL[25] rcol4_512_512x8m81_0/WL[24]
+ rcol4_512_512x8m81_0/WL[23] rcol4_512_512x8m81_0/WL[22] rcol4_512_512x8m81_0/WL[20]
+ rcol4_512_512x8m81_0/WL[27] rcol4_512_512x8m81_0/WL[30] rcol4_512_512x8m81_0/WL[18]
+ rcol4_512_512x8m81_0/WL[41] rcol4_512_512x8m81_0/WL[15] rcol4_512_512x8m81_0/WL[38]
+ rcol4_512_512x8m81_0/WL[45] rcol4_512_512x8m81_0/WL[43] rcol4_512_512x8m81_0/WL[40]
+ rcol4_512_512x8m81_0/WL[39] rcol4_512_512x8m81_0/WL[31] rcol4_512_512x8m81_0/WL[14]
+ rcol4_512_512x8m81_0/WL[16] rcol4_512_512x8m81_0/WL[17] rcol4_512_512x8m81_0/WL[26]
+ rcol4_512_512x8m81_0/WL[19] rcol4_512_512x8m81_0/WL[58] rcol4_512_512x8m81_0/WL[60]
+ rcol4_512_512x8m81_0/WL[62] rcol4_512_512x8m81_0/WL[28] rcol4_512_512x8m81_0/WL[63]
+ rcol4_512_512x8m81_0/WL[21] rcol4_512_512x8m81_0/WL[49] rcol4_512_512x8m81_0/WL[53]
+ rcol4_512_512x8m81_0/WL[47] rcol4_512_512x8m81_0/WL[55] rcol4_512_512x8m81_0/WL[0]
+ rcol4_512_512x8m81_0/WL[2] rcol4_512_512x8m81_0/WL[12] rcol4_512_512x8m81_0/WL[3]
+ rcol4_512_512x8m81_0/WL[4] rcol4_512_512x8m81_0/WL[7] rcol4_512_512x8m81_0/WL[8]
+ rcol4_512_512x8m81_0/WL[9] rcol4_512_512x8m81_0/WL[1] rcol4_512_512x8m81_0/ypass[7]
+ xdec64_512x8m81_0/men rcol4_512_512x8m81_0/WL[5] rcol4_512_512x8m81_0/ypass[0] rcol4_512_512x8m81_0/WL[10]
+ rcol4_512_512x8m81_0/WL[13] rcol4_512_512x8m81_0/ypass[1] rcol4_512_512x8m81_0/ypass[2]
+ rcol4_512_512x8m81_0/ypass[3] rcol4_512_512x8m81_0/ypass[4] rcol4_512_512x8m81_0/ypass[5]
+ rcol4_512_512x8m81_0/ypass[6] rcol4_512_512x8m81_0/WL[6] rcol4_512_512x8m81_0/tblhl
+ rcol4_512_512x8m81_0/GWEN rcol4_512_512x8m81_0/GWE rcol4_512_512x8m81_0/WL[11] rcol4_512_512x8m81_0/pcb[6]
+ rcol4_512_512x8m81_0/pcb[7] rcol4_512_512x8m81_0/pcb[4] rcol4_512_512x8m81_0/vdd
+ WEN[7] WEN[4] rcol4_512_512x8m81_0/pcb[5] WEN[6] WEN[5] D[4] D[7] Q[5] Q[6] Q[7]
+ D[5] D[6] Q[4] xdec64_512x8m81_0/RWL[39] xdec64_512x8m81_0/RWL[56] VSS xdec64_512x8m81_0/RWL[57]
+ xdec64_512x8m81_0/RWL[58] VSS xdec64_512x8m81_0/RWL[59] xdec64_512x8m81_0/RWL[20]
+ xdec64_512x8m81_0/RWL[21] xdec64_512x8m81_0/RWL[22] xdec64_512x8m81_0/RWL[23] xdec64_512x8m81_0/RWL[40]
+ xdec64_512x8m81_0/RWL[24] xdec64_512x8m81_0/RWL[41] rcol4_512_512x8m81_0/saout_R_m2_512x8m81_1/pcb
+ xdec64_512x8m81_0/RWL[25] xdec64_512x8m81_0/RWL[0] xdec64_512x8m81_0/RWL[42] VSS
+ xdec64_512x8m81_0/RWL[26] xdec64_512x8m81_0/RWL[1] xdec64_512x8m81_0/RWL[43] xdec64_512x8m81_0/RWL[60]
+ xdec64_512x8m81_0/RWL[27] xdec64_512x8m81_0/RWL[2] xdec64_512x8m81_0/RWL[44] VSS
+ VSS xdec64_512x8m81_0/RWL[61] xdec64_512x8m81_0/RWL[28] xdec64_512x8m81_0/RWL[3]
+ xdec64_512x8m81_0/RWL[45] xdec64_512x8m81_0/RWL[62] xdec64_512x8m81_0/RWL[29] xdec64_512x8m81_0/RWL[4]
+ xdec64_512x8m81_0/RWL[46] VSS xdec64_512x8m81_0/RWL[63] rcol4_512_512x8m81_0/saout_R_m2_512x8m81_1/pcb
+ VSS xdec64_512x8m81_0/RWL[5] xdec64_512x8m81_0/RWL[47] xdec64_512x8m81_0/RWL[6]
+ xdec64_512x8m81_0/RWL[48] xdec64_512x8m81_0/RWL[7] xdec64_512x8m81_0/RWL[49] xdec64_512x8m81_0/RWL[8]
+ xdec64_512x8m81_0/RWL[9] xdec64_512x8m81_0/RWL[10] xdec64_512x8m81_0/RWL[11] xdec64_512x8m81_0/RWL[12]
+ VSS rcol4_512_512x8m81_0/saout_m2_512x8m81_1/mux821_512x8m81_0/ypass_gate_512x8m81_6/pcb
+ xdec64_512x8m81_0/RWL[13] xdec64_512x8m81_0/RWL[30] rcol4_512_512x8m81_0/saout_R_m2_512x8m81_1/sa_512x8m81_0/pcb
+ xdec64_512x8m81_0/RWL[14] xdec64_512x8m81_0/RWL[31] VSS xdec64_512x8m81_0/RWL[15]
+ VSS xdec64_512x8m81_0/RWL[32] xdec64_512x8m81_0/DRWL xdec64_512x8m81_0/RWL[16] xdec64_512x8m81_0/RWL[33]
+ xdec64_512x8m81_0/RWL[50] xdec64_512x8m81_0/RWL[17] xdec64_512x8m81_0/RWL[34] xdec64_512x8m81_0/RWL[51]
+ xdec64_512x8m81_0/RWL[18] rcol4_512_512x8m81_0/saout_m2_512x8m81_0/mux821_512x8m81_0/ypass_gate_512x8m81_6/pcb
+ xdec64_512x8m81_0/RWL[35] xdec64_512x8m81_0/RWL[52] xdec64_512x8m81_0/RWL[19] xdec64_512x8m81_0/RWL[36]
+ xdec64_512x8m81_0/RWL[53] rcol4_512_512x8m81_0/saout_R_m2_512x8m81_0/sa_512x8m81_0/pcb
+ xdec64_512x8m81_0/RWL[37] xdec64_512x8m81_0/RWL[54] VSS xdec64_512x8m81_0/RWL[38]
+ xdec64_512x8m81_0/RWL[55] VSS WEN[6] rcol4_512_512x8m81
Xxdec64_512x8m81_0 xdec64_512x8m81_0/DRWL xdec64_512x8m81_0/RWL[34] xdec64_512x8m81_0/RWL[35]
+ xdec64_512x8m81_0/RWL[36] xdec64_512x8m81_0/RWL[37] xdec64_512x8m81_0/RWL[38] xdec64_512x8m81_0/RWL[39]
+ xdec64_512x8m81_0/RWL[40] xdec64_512x8m81_0/RWL[42] xdec64_512x8m81_0/RWL[43] xdec64_512x8m81_0/RWL[44]
+ xdec64_512x8m81_0/RWL[45] xdec64_512x8m81_0/RWL[46] xdec64_512x8m81_0/RWL[48] xdec64_512x8m81_0/RWL[50]
+ xdec64_512x8m81_0/RWL[53] xdec64_512x8m81_0/RWL[55] xdec64_512x8m81_0/RWL[57] xdec64_512x8m81_0/RWL[58]
+ xdec64_512x8m81_0/RWL[61] xdec64_512x8m81_0/RWL[62] xdec64_512x8m81_0/RWL[63] xdec64_512x8m81_0/LWL[58]
+ xdec64_512x8m81_0/LWL[56] xdec64_512x8m81_0/LWL[55] xdec64_512x8m81_0/LWL[54] xdec64_512x8m81_0/LWL[53]
+ xdec64_512x8m81_0/LWL[52] xdec64_512x8m81_0/LWL[51] xdec64_512x8m81_0/LWL[50] xdec64_512x8m81_0/LWL[46]
+ xdec64_512x8m81_0/LWL[38] xdec64_512x8m81_0/LWL[36] xdec64_512x8m81_0/LWL[35] xdec64_512x8m81_0/LWL[34]
+ xdec64_512x8m81_0/DLWL xdec64_512x8m81_0/LWL[19] xdec64_512x8m81_0/LWL[20] xdec64_512x8m81_0/LWL[21]
+ xdec64_512x8m81_0/LWL[22] xdec64_512x8m81_0/LWL[27] xdec64_512x8m81_0/LWL[11] xdec64_512x8m81_0/LWL[13]
+ xdec64_512x8m81_0/LWL[15] xdec64_512x8m81_0/LWL[18] xdec64_512x8m81_0/LWL[5] xdec64_512x8m81_0/LWL[4]
+ xdec64_512x8m81_0/LWL[2] xdec64_512x8m81_0/LWL[8] xdec64_512x8m81_0/LWL[9] xdec64_512x8m81_0/LWL[6]
+ xdec64_512x8m81_0/LWL[7] xdec64_512x8m81_0/LWL[29] xdec64_512x8m81_0/RWL[31] xdec64_512x8m81_0/RWL[30]
+ xdec64_512x8m81_0/RWL[6] xdec64_512x8m81_0/RWL[4] xdec64_512x8m81_0/RWL[2] xdec64_512x8m81_0/RWL[0]
+ xdec64_512x8m81_0/RWL[1] xdec64_512x8m81_0/RWL[3] xdec64_512x8m81_0/RWL[5] xdec64_512x8m81_0/RWL[7]
+ xdec64_512x8m81_0/RWL[8] xdec64_512x8m81_0/RWL[10] xdec64_512x8m81_0/RWL[12] xdec64_512x8m81_0/RWL[14]
+ xdec64_512x8m81_0/RWL[15] xdec64_512x8m81_0/RWL[16] xdec64_512x8m81_0/RWL[17] xdec64_512x8m81_0/xb[0]
+ xdec64_512x8m81_0/xb[1] xdec64_512x8m81_0/xb[2] xdec64_512x8m81_0/xb[3] xdec64_512x8m81_0/xa[7]
+ xdec64_512x8m81_0/xa[6] xdec64_512x8m81_0/xa[5] xdec64_512x8m81_0/xa[4] xdec64_512x8m81_0/xa[0]
+ xdec64_512x8m81_0/xa[3] xdec64_512x8m81_0/xa[1] xdec64_512x8m81_0/xc[0] xdec64_512x8m81_0/xc[1]
+ xdec64_512x8m81_0/LWL[44] xdec64_512x8m81_0/LWL[42] xdec64_512x8m81_0/LWL[25] xdec64_512x8m81_0/LWL[40]
+ xdec64_512x8m81_0/RWL[41] xdec64_512x8m81_0/LWL[23] xdec64_512x8m81_0/LWL[49] xdec64_512x8m81_0/RWL[60]
+ xdec64_512x8m81_0/RWL[59] xdec64_512x8m81_0/LWL[62] xdec64_512x8m81_0/men xdec64_512x8m81_0/LWL[60]
+ xdec64_512x8m81_0/RWL[29] xdec64_512x8m81_0/LWL[47] xdec64_512x8m81_0/RWL[27] xdec64_512x8m81_0/LWL[48]
+ xdec64_512x8m81_0/LWL[45] xdec64_512x8m81_0/RWL[25] xdec64_512x8m81_0/LWL[0] xdec64_512x8m81_0/LWL[30]
+ xdec64_512x8m81_0/LWL[63] xdec64_512x8m81_0/LWL[28] xdec64_512x8m81_0/LWL[43] xdec64_512x8m81_0/LWL[26]
+ xdec64_512x8m81_0/RWL[23] xdec64_512x8m81_0/LWL[24] xdec64_512x8m81_0/LWL[33] xdec64_512x8m81_0/LWL[3]
+ xdec64_512x8m81_0/RWL[28] xdec64_512x8m81_0/LWL[61] xdec64_512x8m81_0/RWL[13] xdec64_512x8m81_0/RWL[26]
+ xdec64_512x8m81_0/LWL[41] xdec64_512x8m81_0/LWL[32] xdec64_512x8m81_0/RWL[24] xdec64_512x8m81_0/RWL[51]
+ xdec64_512x8m81_0/RWL[21] xdec64_512x8m81_0/RWL[32] xdec64_512x8m81_0/xa[2] xdec64_512x8m81_0/RWL[22]
+ xdec64_512x8m81_0/RWL[33] xdec64_512x8m81_0/LWL[1] xdec64_512x8m81_0/RWL[20] xdec64_512x8m81_0/LWL[59]
+ xdec64_512x8m81_0/RWL[18] xdec64_512x8m81_0/RWL[11] xdec64_512x8m81_0/LWL[39] xdec64_512x8m81_0/LWL[16]
+ xdec64_512x8m81_0/RWL[49] xdec64_512x8m81_0/RWL[19] xdec64_512x8m81_0/LWL[14] xdec64_512x8m81_0/LWL[31]
+ xdec64_512x8m81_0/LWL[12] xdec64_512x8m81_0/RWL[56] xdec64_512x8m81_0/LWL[57] xdec64_512x8m81_0/LWL[10]
+ xdec64_512x8m81_0/RWL[9] VSS xdec64_512x8m81_0/LWL[37] xdec64_512x8m81_0/RWL[54]
+ VSS xdec64_512x8m81_0/RWL[52] xdec64_512x8m81_0/RWL[47] xdec64_512x8m81_0/LWL[17]
+ xdec64_512x8m81
Xcontrol_512x8_512x8m81_0 VSS VSS rcol4_512_512x8m81_0/ypass[7] rcol4_512_512x8m81_0/ypass[6]
+ rcol4_512_512x8m81_0/ypass[5] rcol4_512_512x8m81_0/ypass[4] rcol4_512_512x8m81_0/ypass[3]
+ rcol4_512_512x8m81_0/ypass[2] rcol4_512_512x8m81_0/ypass[1] rcol4_512_512x8m81_0/ypass[0]
+ control_512x8_512x8m81_0/LYS[0] control_512x8_512x8m81_0/LYS[1] control_512x8_512x8m81_0/LYS[2]
+ control_512x8_512x8m81_0/LYS[3] control_512x8_512x8m81_0/LYS[6] control_512x8_512x8m81_0/LYS[5]
+ control_512x8_512x8m81_0/LYS[4] control_512x8_512x8m81_0/LYS[7] control_512x8_512x8m81_0/tblhl
+ rcol4_512_512x8m81_0/GWE GWEN rcol4_512_512x8m81_0/GWEN xdec64_512x8m81_0/xb[3]
+ xdec64_512x8m81_0/xb[2] xdec64_512x8m81_0/xb[0] xdec64_512x8m81_0/xb[1] control_512x8_512x8m81_0/xc[3]
+ xdec64_512x8m81_0/xc[1] control_512x8_512x8m81_0/xc[2] xdec64_512x8m81_0/xc[0] VSS
+ A[7] CLK A[6] A[3] A[4] A[5] A[8] VSS CEN control_512x8_512x8m81_0/LYS[0] control_512x8_512x8m81_0/LYS[1]
+ control_512x8_512x8m81_0/LYS[2] control_512x8_512x8m81_0/LYS[3] control_512x8_512x8m81_0/LYS[4]
+ control_512x8_512x8m81_0/LYS[5] control_512x8_512x8m81_0/LYS[6] control_512x8_512x8m81_0/LYS[7]
+ xdec64_512x8m81_0/xa[0] xdec64_512x8m81_0/xa[1] xdec64_512x8m81_0/xa[2] xdec64_512x8m81_0/xa[3]
+ A[0] xdec64_512x8m81_0/xa[4] A[1] xdec64_512x8m81_0/xa[5] A[2] xdec64_512x8m81_0/xa[6]
+ xdec64_512x8m81_0/xa[7] VSS VSS xdec64_512x8m81_0/men rcol4_512_512x8m81_0/tblhl
+ VSS control_512x8_512x8m81
.ends

extraction script:

set extdir $::env(ext_out)/tmp_ext
file mkdir $extdir
cd $extdir
crashbackups stop
drc off
gds flatten yes
gds read $::env(ext_inp1)
load [file rootname [file tail $::env(ext_inp1)]] -dereference
extract no all
extract do local
extract
ext2spice lvs
ext2spice -o $::env(ext_out)/[file rootname [file tail $::env(ext_inp1)]]-gds-extracted.spice
exit
jeffdi commented 1 year ago

duplicate of #87