porb does not affect SoC

[RTimothyEdwards]

The "porb" signal from the power-on-reset circuit is input to housekeeping only; it does not affect operation of the SoC or any other circuit on the chip at all. This is caused by the direct derivation of the architecture from the sky130 version, where all pads have a power-on-reset input and this gates the operation of the reset pin which in turn gates operation of the SoC. The GF version has no power-on-reset input to the pads, so the SoC needs to be gated by "porb" directly.

Solution is in pull request #78, which is to make "porb" an input to the SoC, specifically to the caravel_clocking block, which combines it with the reset pin and the manual reset signal from the housekeeping SPI.

[RTimothyEdwards]

This is a duplicate of #76.