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efabless / caravel

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
https://caravel-harness.readthedocs.io/
Apache License 2.0
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1.8V buffer on 3.3V signal. #302

Closed d-m-bailey closed 1 year ago

d-m-bailey commented 1 year ago

/por/porb_h, a 3.3V signal is passed through a 1.8V buffer /Xsoc(mgmt_core_wrapper)/Xinput207(PX_sky130_fd_sc_hd__clkbuf_16) before being sent as /soc/porb_h_out to the gpio/xres blocks, which appear to be expecting a 3.3V signal.

d-m-bailey commented 1 year ago

With caravel_redesign branch: commit bbb6bf775c6c2c31376d5992906f929953aaef0b using scripts/signoff_automation.py to create caravel.gds, it appears that 3.3V porb_h in to 1.8V soc buffer has been fixed.

net trace of simple_por output shows connections directly to gpio cells and no connections to soc.

RTimothyEdwards commented 1 year ago

This has been done and is correct in the top level layout, although I can't find the specific pull request for it.

passant5 commented 1 year ago

Fixed here: https://github.com/efabless/caravel/issues/273

azwefabless commented 1 year ago

This was completed as a direct commit to caravel_redesign. Not best practice but is done.