LVS: caravan missing or outdated gate level verilog

[d-m-bailey]

Missing verilog/gl/gpio_signal_buffering_alt.v.

verilog/gl/chip_io_alt.v is 11 months old and does not have the recent constant_block additions.

[RTimothyEdwards]

@marwaneltoukhy or @kareefardi (@shalan ): We need the verilog taken through the flow to get gate level views of these cells the same way that was done for the equivalent cells in caravel (gpio_signal_buffering and chip_io).