Logic analyzer "sample" function does not do anything useful

[RTimothyEdwards]

The "sample" bit on the logic analyzer was intended to simultaneously capture (up to) all 128 bits of the logic analyzer, because otherwise it would require four passes to capture and read 32 signals at a time. The implementation is that the "la_data" output register is used to capture the input signal, under the assumption that the signal is configured to be an input, so the "la_data" output register is otherwise unused. However, the logic analyzer implementation only writes to the "la_data" register and always reads from the non-registered "la_data_in" signals. So there is no way to read back the captured data.

The simplest fix would be to add an additional control bit which would be used to multiplex the read-back between "la_data" and "la_data_in". That would allow the sampled bits to be read back by the management SoC.

Also: The implementation of the "sample" bit should be changed so that it is a self-resetting bit. It should cause the data to be sampled once and only once on the rising edge of the "sample" register value.

Possibly a better overall implementation would be to have an array of transparent latches at the data inputs and outputs. The "enable" line on all input latches would be shared, and the "enable" line of all output latches would be shared. That would add a bit of overhead circuitry, but all 128 bits of the logic analyzer could be captured simultaneously, and also all 128 bits of output could be set simulaneously. There would be no need to repurpose the output register as an input buffer.

[blue67chillout]

it would be great if u guys add the logic analyser and wishbone in docs as soon as possibel